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CLK1
DA[15:0]
DB[15:0]
t
s(DATA)
t
h(DATA)
A
0
A
1
A
2
A
N
A
N+1
A
3
B
0
B
1
B
2
B
N
B
N+1
B
3
T0039-01
B0053-09
CLK
Buffer
CLK
Buffer
PFD
Charge
Pump
VCO
/1
/2
/4
/8
00
01
10
11
1
0
/2
Data
Latch
1 ´2
´1
0
00
01
10
11
/2
/2
0
1
CLK1
CLK1C
CLK2
LPF
pll_div(1:0)
PLLVDD
PLLLOCK
PLLVDD
DA[15:0]
DB[15:0]
interl
interp(1:0)
f
DAC
f /2X2
DAC
f /4
DAC
X4
f /4
DAC
X4L
f /8
DAC
X8
Data
Lock
CLK2C
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
A type-four phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback
clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated
by dividing the VCO output by 1 × , 2 × , 4 × , or 8 × as selected by the prescaler div(1:0). The output of the prescaler
is the DAC sample rate clock and is divided down to generate clocks at ÷ 2, ÷ 4, and ÷ 8. The feedback clock is
selected by the registers sel(1:0), which is fed back to the PFD for synchronization to the input clock. The
feedback clock is also used for the data input rate, so the ratio of DAC output clock to feedback clock sets the
interpolation rate of the DAC5687. The PLLLOCK pin is an output indicating when the PLL has achieved lock. An
external RC low-pass PLL filter is provided by the user at pin LPF. See the Low-Pass Filter section for
filter-setting calculations. This is the only mode where the LPF filter applies.
Figure 45. Dual-Bus Mode Timing Diagram (PLL Mode)
Figure 46. Clock Generation Architecture in PLL Mode
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