Datasheet

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CLK2

DA[15:0]

DB[15:0]

s(DATA)

h(DATA)

N+1

PLLLOCK

d(PLLLOCK)

T0040-01

CLK2

DA[15:0]

DB[15:0]

s(DATA)

h(DATA)

N+1

PLLLOCK

d(PLLLOCK)

T0040-02

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through

CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used. The LPF and CLK1/CLK1C pins can be left

unconnected. The input data-rate clock and interpolation rate are selected by the bits interp(1:0) in register

CONFIG0 and is output through the PLLLOCK pin. The PLLLOCK clock can be used to drive the input data

source (such as digital upconverter) that sends the data to the DAC. Note that the PLLLOCK delay relative to the

input CLK2 rising edge (t

d(PLLLOCK)

in Figure 43 and Figure 44 ) increases with increasing loads. The PLLLOCK

output driver is not capable of reaching full speed at lower IOVDD voltages. For example, at IOVDD = 1.8 V,

PLLLOCK output frequencies > 100 MHz are not recommended. The input data is latched on either the rising

( inv_plllock = 0) or falling edge ( inv_plllock = 1) of PLLLOCK, which is sensed internally at the output pin.

Figure 43. Dual-Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Rising Edge)

Figure 44. Dual-Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Falling Edge)

2. PLLVDD = 3.3 V ( dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE

In PLL CLOCK MODE, drive the DAC at the input sample rate (unless the data is multiplexed) through

CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC

generates the higher-speed DAC sample-rate clock using an internal PLL/VCO. In PLL clock mode, the user

provides a differential external reference clock on CLK1/CLK1C.

Product Folder Link(s): DAC5687