Datasheet

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Register Name: CONFIG0 — Address: 0x01, Default = 0x00
Register Name: CONFIG1 — Address: 0x02, Default = 0x00
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
BIT 7 BIT 0
pll_div(1:0) pll_freq pll_kv interp(1:0) inv_plllock fifo_bypass
0 0 0 0 0 0 0 0
pll_div(1:0): PLL VCO divider; {00 = 1, 01 = 2, 10 = 4, 11 = 8}.
pll_freq: PLL VCO center frequency; {0 = low center frequency, 1 = high center frequency}.
pll_kv: PLL VCO gain; {0 = high gain, 1 = low gain}.
interp(1:0): FIR interpolation; {00 = X2, 01 = X4, 10 = X4L, 11 = X8}. X4 uses lower power than X4L, but f
DAC
=
320 MHz maximum when NCO or QMC is used.
inv_plllock: Multifunction bit, depending on clock mode
fifo_bypass: When set, the internal four-sample FIFO is disabled. When cleared, the FIFO is enabled.
Table 2. inv_plllock Bit Modes
PLLVDD dual_clk inv_plllock fifo_bypass DESCRIPTION
0 V 0 0 1 Input data latched on PLLLOCK pin rising edges, FIFO disabled
0 V 0 1 1 Input data latched on PLLLOCK pin falling edges, FIFO disabled
0 V 0 0 0 Input data latched on PLLLOCK pin rising edges, FIFO enabled
and must be synchronized
0 V 0 1 0 Input data latched on PLLLOCK pin falling edges, FIFO enabled
and must be synchronized
0 V 1 0 1 Input data latched on CLK1/CLK1C differential input. Timing
between CLK1 and CLK2 rising edges must be tightly controlled
(500 ps maximum at 500-MHz CLK2). PLLLOCK output signal is
always low. The FIFO is always disabled in this mode.
0 V 1 1 0 Input data latched on CLK1/CLK1C differential input. No phase
relationship required between CLK1 and CLK2. The FIFO is
employed to manage the internal handoff between the CLK1
input clock and the CLK2 derived output clock; the FIFO must
be synchronized. The PLLLOCK output signal reflects the
internally generated FIFO output clock.
0 V 1 0 0 Not a valid setting. Do not use.
0 V 1 1 1 Not a valid setting. Do not use.
3.3 V X X 1 Internal PLL enabled, CLK1/CLK1C input differential clock is
used to latch the input data. The FIFO is always disabled in this
mode.
3.3 V X X 0 Not a valid setting. Do not use.
BIT 7 BIT 0
qflag interl dual_clk twos rev_abus rev_bbus fir_bypass full_bypass
0 0 0 0 0 0 0 0
qflag: When set, the QFLAG input pin operates as a B sample indicator when interleaved data is enabled. When
cleared, the TXENABLE rising determines the A/B timing relationship.
interl: When set, interleaved input data mode is enabled; both A and B data streams are input at the DA[15:0]
input pins.
dual_clk: Only used when the PLL is disabled. When set, two differential clocks are used to input the data to the
chip; CLK1/CLK1C is used to latch the input data into the chip and CLK2/CLK2C is used as the DAC
sample clock.
twos: When set, input data is interpreted as 2s complement. When cleared, input data is interpreted as offset
binary.
rev_abus: When cleared, DA input data MSB to LSB order is DA[15] = MSB and DA[0] = LSB. When set, DA
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