Datasheet

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y2y2
CLK1
CLK1C
LPF
PLLLOCK
CLKVDD CLKGND DVDD DGNDPLLVDDPLLGND SLEEP
FIR1
sin
IOVDD
IOGND
AVDD AGND
PHSTR
NCO
cosRESETB
100-Pin HTQFP
EXTIO
EXTLO
1.2-V
Reference
BIASJ
IOUTA1
IOUTA2
16-Bit
FIR4
IOUTB1
IOUTB2
FIR2
x
sin(x)
TXENABLE
DA[15:0]
DB[15:0]
CLK2
CLK2C
SIF
SCLKSDENBSDOSDIO
DAC
16-Bit
DAC
2y–8y f
DATA
Internal Clock Generation
and
2y–8y PLL Clock Multiplier
x
sin(x)
A Gain
B Gain
A
Offset
B
Offset
B0019-02
QFLAG
Input FIFO/
Reorder/
Mux/Demux
Fine Mixer
Quadrature Mod
Correction (QMC)
y2y2
y2
FIR3
Course Mixer:
fs/2 or fs/4
y2
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
2 Submit Documentation Feedback Copyright © 2005 – 2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687