Datasheet

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CLK1
CLK1C
LPF
PLLLOCK
DGND
PLLVDD
PLLGND
SLEEP
IOGND
IOVDD
AVDD
AGND
PHSTR
RESETB
EXTIO
EXTLO
BIASJ
IOUTA1
IOUTA2
IOUTB1
IOUTB2
TXENABLE
DA[15:0]
DB[15:0]
C
EXTIO
0.1 µF
R
BIAS
1 kΩ
3.3 V
3.3 V
100 Ω
HP8665B
Synthesized
Signal
Generator
1:4
Mini Circuits
TCM4−1W
200 Ω
0.01 µF
16
Agilent 16702B
Mainframe System
With
16720A Pattern
Generator Card
Rohde & Schwarz
FSQ8
Spectrum
Analyzer
PULSE
FREQ. = f
data
93.1 Ω
0.033 µF
330 pF
CLKVDD
CLKGND
Agilent 8133A
Pulse Generator
CLK2
CLK2C
DVDD
(Not Including Pin 56)
1.8 V/2.1 V
10 Ω
10 pF
DVDD
(Pin 56)
3.3 V
16
PULSE
FREQ. = f
data
Ampl. = 1 V
PP
1:4
Mini Circuits
T4−1
3.3 V
3.3 V
100 Ω
3.3 V
Sinusoid
FREQ. = f
data
B0039-02
3.3 V
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 27. DAC5687 Test Configuration for PLL Clock Mode
WCDMA test-model-1 test vectors for the DAC5687 characterization were generated in accordance with the
3GPP Technical Specification. Chip-rate data was generated using the test-model-1 block in the Agilent ADS.
For multicarrier signals, different random seeds and PN offsets were used for each carrier. A Matlab™ script
performed pulse shaping, interpolation to the DAC input data rate, frequency offsets, rounding, and scaling. Each
test vector is 10 ms long, representing one frame. Special care is taken to assure that the end of the file wraps
smoothly to the beginning of the file.
The cumulative complementary distribution function (CCDF) for the 1-, 2-, and 4-carrier test vectors is shown in
Figure 28 . The test vectors are scaled such that the absolute maximum data point is 0.95 ( – 0.45 dB) of full scale.
No peak reduction is used.
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