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CLK2
CLK2C
LPF
PLLLOCK
DGND
PLLVDD
PLLGND
SLEEP
IOGND
IOVDD
AVDD
AGND
PHSTR
RESETB
EXTIO
EXTLO
BIASJ
IOUTA1
IOUTA2
IOUTB1
IOUTB2
TXENABLE
DA[15:0]
DB[15:0]
C
EXTIO
0.1 µF
R
BIAS
1 kΩ
3.3 V
3.3 V
100 Ω
HP8665B
Synthesized
Signal
Generator
1:4
Mini Circuits
TCM4−1W
200 Ω
0.01 µF
16
Agilent 16702B
Mainframe System
With
16720A Pattern
Generator Card
Rohde & Schwarz
FSQ8
Spectrum
Analyzer
PULSE
FREQ. = f
data
93.1 Ω
0.033 µF
330 pF
CLKVDD
CLKGND
Agilent 8133A
Pulse Generator
CLK1
CLK1C
DVDD
(Not Including Pin 56)
1.8 V/2.1 V
10 Ω
10 pF
DVDD
(Pin 56)
3.3 V
16
PULSE
FREQ. = f
DAC
Ampl. = 1 V
PP
1:4
Mini Circuits
T4−1
3.3 V
3.3 V
100 Ω
3.3 V
Sinusoid
FREQ. = f
DAC
B0039-01
3.3 V
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 26. DAC5687 Test Configuration for External Clock Mode
PLL clock mode was characterized using the test configuration shown in Figure 27 . The DAC data rate clock
f
DATA
is generated by an HP8665B signal generator. An Agilent 8133A pulse generator is used to generate a
clock f
DATA
for the Agilent 16702A pattern-generator clock and provide adjustable skew to the DAC input clock.
The 8133A f
DAC
output is set to 1 V
PP
, equivalent to 2-V
PP
differential at CLK1/CLK1C pins. Alternatively, the
DAC5687 PLLLOCK output can be used for the pattern-generator clock.
18 Submit Documentation Feedback Copyright © 2005 – 2006, Texas Instruments Incorporated
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