Datasheet

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CLK2
1
0.5
2f
-
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUT
FS
= 19.2 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLL
At 600-kHz offset, measured at DAC output,
25-MHz, 0-dBFS tone, f
DATA
= 125 MSPS, 133
4 × interpolation, pll_freq = 1, pll_kv = 0
Phase noise dBc/Hz
At 6-MHz offset, measured at DAC output,
25 MHz 0-dBFS tone, 125 MSPS, 148.5
4 × interpolation, pll_freq = 1, pll_kv = 0
pll_freq = 0, pll_kv = 1 370
pll_freq = 0, pll_kv = 0 480
VCO maximum frequency MHz
pll_freq = 1, pll_kv = 1 495
pll_freq = 1, pll_kv = 0 520
pll_freq = 0, pll_kv = 1 225
pll_freq = 0, pll_kv = 0 200
VCO minimum frequency MHz
pll_freq = 1, pll_kv = 1 480
pll_freq = 1, pll_kv = 0 480
NCO and QMC BLOCKS
QMC clock rate 320 MHz
NCO clock rate 320 MHz
SERIAL PORT TIMING
t
s(SDENB)
Setup time, SDENB to rising edge of SCLK 20 ns
Setup time, SDIO valid to rising edge of
t
s(SDIO)
10 ns
SCLK
Hold time, SDIO valid to rising edge of
t
h(SDIO)
5 ns
SCLK
t
SCLK
Period of SCLK 100 ns
t
SCLKH
High time of SCLK 40 ns
t
SCLK
Low time of SCLK 40 ns
Data output delay after falling edge of
t
d(Data)
10 ns
SCLK
CLOCK INPUT (CLK1/CLK1C, CLK2/CLK2C)
Duty cycle 40% 60%
Differential voltage 0.4 1 V
TIMING PARALLEL DATA INPUT: CLK1 LATCHING MODES
(PLL Mode – See Figure 45 , Dual Clock Mode FIFO Disabled – See Figure 47 , Dual Clock Mode With FIFO Enabled – See Figure 48 )
Setup time, DATA valid to rising edge of
t
s(DATA)
0.5 ns
CLK1
Hold time, DATA valid after rising edge of
t
h(DATA)
1.5 ns
CLK1
Maximum offset between CLK1 and CLK2
t_align rising edges – dual clock mode with FIFO ns
disabled
Timing Parallel Data Input (External Clock Mode, Latch on PLLLOCK Rising Edge, CLK2 Clock Input, See Figure 43 )
Setup time, DATA valid to rising edge of
t
s(DATA)
72- Ω load on PLLLOCK 0.5 ns
PLLLOCK
Hold time, DATA valid after rising edge of
t
h(DATA)
72- Ω load on PLLLOCK 1.5 ns
PLLLOCK
Delay from CLK2 rising edge to PLLLOCK 72- Ω load on PLLLOCK. Note that PLLLOCK
t
delay(Plllock)
4.5 ns
rising edge delay increases with a lower-impedance load.
Timing Parallel Data Input (External Clock Mode, Latch on PLLLOCK Falling Edge, CLK2 Clock Input, See Figure 44 )
Setup time, DATA valid to falling edge of
t
s(DATA)
High-impedance load on PLLLOCK 0.5 ns
PLLLOCK
Hold time, DATA valid after falling edge of
t
h(DATA)
High-impedance load on PLLLOCK 1.5 ns
PLLLOCK
High-impedance load on PLLLOCK. Note that
Delay from CLK2 rising edge to PLLLOCK
t
delay(Plllock)
PLLLOCK delay increases with a 4.5 ns
rising edge
lower-impedance load.
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