Datasheet

IOUT1
1:1
IOUT2
50 Ω
50 Ω
R
LOAD
50 Ω
100 Ω
AVDD (3.3 V)
AVDD (3.3 V)
S0033-01
IOUT1
4:1
IOUT2
100 Ω
100 Ω
R
LOAD
50 Ω
AVDD (3.3 V)
AVDD (3.3 V)
S0033-02
SLEEP MODE
POWER-UP SEQUENCE
DAC5686
www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009
Figure 51. Driving a Doubly Terminated 50- Ω Cable Using a 1:1 Impedance-Ratio Transformer
Figure 52. Driving a Doubly Terminated 50- Ω Cable Using a 4:1 Impedance-Ratio Transformer
The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of – 40C to 85C. The power-down
mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An
internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected.
Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a
nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up.
In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): DAC5686