Datasheet

R
T
200 Ω
CLK
1:4
CLKC
Termination Resistor
Swing Limitation
Optional, May Be Bypassed
for Sine Wave Input
C
AC
0.1 µF
S0029-01
R
opt
22 Ω
CLK
1:1
CLKC
Optional, Reduces
Clock Feedthrough
C
AC
0.01 µF
TTL/CMOS
Source
R
opt
22 Ω
CLK
CLKC
Node CLKC Internally Biased
to CLKVDDń2
TTL/CMOS
Source
0.01 µF
S0030-01
R
T
130 Ω
C
AC
0.1 µF
C
AC
0.1 µF
R
T
130 Ω
V
TT
Differential
ECL
or
(LV)PECL
Source
+
–
CLK
CLKC
R
T
82.5 Ω
R
T
82.5 Ω
100 Ω
S0031-01
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com
Figure 47. Preferred Clock Input Configuration
Figure 48. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source
Figure 49. Driving the DAC5686 With a Differential ECL/PECL Clock Source
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Product Folder Link(s): DAC5686