Datasheet

DAC5686
www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009
freq_int[23:16]: The upper mid 8 bits of the frequency register in the DDS block
Register Name: freq_msb
MSB LSB
freq_int[31:24]
0 0 1 0 0 0 0 0
freq_int[31:24]: The most significant 8 bits of the frequency register in the DDS block
Register Name: phase_lsb
MSB LSB
phase_int[7:0]
0 0 0 0 0 0 0 0
phase_int[7:0]: The lower 8 bits of the phase register in the DDS block
Register Name: phase_msb
MSB LSB
phase_int[15:8]
0 0 0 0 0 0 0 0
phase_int[15:8]: The most significant 8 bits of the phase register in the DDS block
Register Name: config_lsb
MSB LSB
mode[1:0] div[1:0] sel[1:0] counter Full_bypass
0 0 0 0 0 0 0 1
mode[1:0]: Controls the mode of the DAC5686; summarized in Table 6 .
Table 6. DAC5686 Modes
mode[1:0] DAC5686 MODE
00 Dual-DAC
01 Single-sideband
10 Quadrature
11 Dual-DAC
div[1:0]: Controls the PLL divider value; summarized in Table 7 .
Table 7. PLL Divide Ratios
div[1:0] PLL DIVIDE RATIO
00 1 × divider
01 2 × divider
10 4 × divider
11 8 × divider
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