Datasheet

DA[15:0]
t
s(DATA)
t
h(DATA)
A
0
B
0
A
1
A
N
B
N
B
1
TXENABLE
t
s(TXENABLE)
CLK1 or
PLLLOCK
T0041-01
DA[15:0]
t
s(DATA)
t
h(DATA)
A
0
B
0
A
1
A
N
B
N
B
1
QFLAG
CLK1 or
PLLLOCK
T0001-01
Clock Synchronization Using the PHSTR Pin in External Clock Mode
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com
Figure 35. Interleave Bus Mode Timing Diagram Using TxENABLE
Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels
A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register
config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising
edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed
to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an input
by the user to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 36 ).
Figure 36. Interleave Bus Mode Timing Diagram Using QFLAG
When using interleaved input mode with the PLL enabled, the input clock CLK1 is at 2 × the frequency of the
input to FIR1. The divider that generates the clock for the FIR1 input cannot be synchronized between multiple
DAC5686s, which can result in a one-CLK1-period output time difference between devices that have
synchronized input data. Dual-clock mode is recommended in applications where multiple DAC5686s must be
synchronized in interleaved input mode.
The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686
uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges
of the two input clocks must be phase-aligned within 500 ps to function properly.
In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an
interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 37 for
N = 4).
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