Datasheet
CLK1
DA[15:0]
DB[15:0]
t
s(DATA)
t
h(DATA)
A
0
A
1
A
2
A
N
A
N+1
A
3
B
0
B
1
B
2
B
N
B
N+1
B
3
T0039-01
CLK2
DA[15:0]
DB[15:0]
t
s(DATA)
t
h(DATA)
A
0
A
1
A
2
A
N
A
N+1
A
3
B
0
B
1
B
2
B
N
B
N+1
B
3
PLLLOCK
t
d(PLLLOCK)
T0040-01
Interleave Bus Mode
IOUTB1
IOUTB2
IOUTA1
IOUTA2
16-Bit
DAC
2f
DATA
2y–16y f
DATA
f
DATA
y2
16-Bit
DAC
2f
DATA
y2
FIR1
Edge Triggered
Input Latches
• • •
• • •
DA[15:0]
DEMUX
B0025-02
DAC5686
www.ti.com
............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009
Figure 32. Dual-Bus Mode Timing Diagram (PLL Mode)
Figure 33. Dual-Bus Mode Timing Diagram (External Clock Mode)
In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data
bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 34 shows
the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 35 .
Figure 34. Interleave Bus Mode Data Path
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