Datasheet

PLLVDD
PLLGND
CLKGND
CLKVDD
PFD
Charge
Pump
VCO
/1
/2
/4
/8
D[15:0]
DIV[1:0] PLLVDD
SEL[1:0]PLLVDDPLLLOCK
LPF
s
1
0
/2
/2
/2
/2
CLK1
CLK1C
Clk Buffer
CLK2
CLK2C
Clk Buffer
B0024-01
clk_16y
DAC
Sample
Clock
clk_8y
clk_4y
clk_2y
clk_1y
Data
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com
Figure 27. Clock-Generation Architecture
Table 3. Clock-Mode Configuration
CLOCK MODE PLLVDD DIV[1:0] SEL[1:0] DATA RATE (MSPS) PLLLOCK PIN FUNCTION
Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate.
External 2 × 0 V XX 00 DC to 160 External clk2/clk2c clock ÷ 2
External 4 × 0 V XX 01 DC to 125 External clk2/clk2c clock ÷ 4
External 8 × 0 V XX 10 DC to 62.5 External clk2/clk2c clock ÷ 8
External 16 × 0 V XX 11 DC to 31.25 External clk2/clk2c clock ÷ 16
External dual clock 2 × 0 V XX 00 DC to 160 None - held low
External dual clock 4 × 0 V XX 01 DC to 125 None - held low
External dual clock 8 × 0 V XX 10 DC to 62.5 None - held low
External dual clock 16 × 0 V XX 11 DC to 31.25 None - held low
Interleaved input data on the DA[15:0] input pins; internal PLL off
External 2 × 0 V XX 00 DC to 80 External clk2/clk2c clock ÷ 2
External 4 × 0 V XX 01 DC to 80 External clk2/clk2c clock ÷ 4
External 8 × 0 V XX 10 DC to 62.5 External clk2/clk2c clock ÷ 8
External 16 × 0 V XX 11 DC to 31.25 External clk2/clk2c clock ÷ 16
External dual clock 2 × 0 V XX 00 DC to 80 None - held low
External dual clock 4 × 0 V XX 01 DC to 62.5 None - held low
External dual clock 8 × 0 V XX 10 DC to 31.25 None - held low
External dual clock 16 × 0 V XX 11 DC to 15.625 None - held low
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