Datasheet

R/W
D7
SDENB
SCLK
SDIO N1 N0 − A3 A2 A1 A0 D6 D5 D4 D3 D2 D0 0
Instruction Cycle
Data Transfer Cycle(s)
SDO D7 D6 D5 D4 D3 D2 D1 D0
0
3-Pin Configuration
Output
4-Pin Configuration
Output
SDENB
SCLK
SDIO
Data n Data n−1
SDO
t
d(DATA)
D1
T0038-01
Clock Generation
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the
data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from
the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin
configuration.
Figure 25. Serial-Interface Read Timing Diagram
In the DAC5686, the internal clocks (1 × , 2 × , 4 × , 8 × , and 16 × , as needed) for the logic, FIR interpolation filters,
and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the
DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is
separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise
within the PLL.
The DAC5686 has three clock modes for generating the internal clocks (1 × , 2 × , 4 × , 8 × , and 16 × , as needed) for
the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in
register config_usb. A block diagram for the clock generation circuit is shown in Figure 27 .
1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE
In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through
CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input
data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the
PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC;
otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and
an external clock divider divides down. (For a divide-by-N, there are N possible phases.) The phase
ambiguity can also be solved by using PHSTR pin with a synchronization signal.
2. PLLVDD = 3.3 V ( dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE
Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock
generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise.
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