Datasheet

Serial-Port Timing Diagrams
R/W
t
(SCLKL)
SDENB
SCLK
SDIO N1 N0 − A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDENB
SCLK
SDIO
Instruction Cycle Data Transfer Cycle(s)
t
s(SDENB)
t
(SCLK)
t
h(SDIO)
t
s(SDIO)
t
(SCLKH)
T0037-01
DAC5686
www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009
Table 1. Instruction Byte of the Serial Interface (continued)
MSB LSB
Description R/ W N1 N0 – A3 A2 A1 A0
R/ W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation
from the DAC5686 and a low indicates a write operation to the DAC5686.
N[1:0]: Identifies the number of data bytes to be transferred per Table 2 . Data is transferred MSB-first.
Table 2. Number of Transferred Bytes Within One
Communication Frame
N1 N0 DESCRIPTION
0 0 Transfer 1 byte
0 1 Transfer 2 bytes
1 0 Transfer 3 bytes
1 1 Transfer 4 bytes
A4: Unused
A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte
transfers, this address is the starting address and the address decrements. Note that the address is written to the
DAC5686 MSB-first.
Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK.
Figure 24. Serial-Interface Write Timing Diagram
Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface
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