Datasheet
FIR1 FIR2 FIR3 FIR4
IOUTB1
IOUTB2
16-Bit
DAC
DA[15:0]
DB[15:0]
2y–16y f
DATA
f
DATA
y2
B Gain
B
Offset
FIR1 FIR2 FIR3 FIR4
y2
y2
y2
y2
y2
y2
y2
FIR5
x
sin(x)
+
+/−
cos sin
sin cos
DEMUX
B0023-01
Serial Interface
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................
www.ti.com
Figure 23. Data Path in Quadrature Modulation Mode
In quadrature modulation mode, only one output from the complex mixer stage is routed to the B DAC. The
output can be expressed as:
B(t) = I(t)sin( ω
c
t) + Q(t)cos( ω
c
t)
or
B(t) = I(t)cos( ω
c
t) – Q(t)sin( ω
c
t)
Single-sideband up-conversion is achieved when I and Q are Hilbert transform pairs. Upper- or lower-sideband
up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that
is routed out.
The offset and gain features for the B DAC, as previously described, are functional in the quadrature mode.
The serial port of the DAC5686 is a flexible serial interface that communicates with industry-standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of the DAC5686. It is compatible with most synchronous transfer formats and can be configured
as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial-interface
input clock and SDENB is the serial-interface enable. For the 3-pin configuration, SDIO is a bidirectional pin for
both data-in and data-out. For the 4-pin configuration, SDIO is data-in only and SDO is data-out only.
Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1 – 4 bytes). The first frame byte is the instruction cycle, which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from
which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred.
Table 1. Instruction Byte of the Serial Interface
MSB LSB
Bit 7 6 5 4 3 2 1 0
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