Datasheet
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)
(1)
DAC5686
SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUT
FS
= 20 mA, external clock mode, differential transformer-coupled output, 50- Ω doubly terminated load (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
DATA
= 160 MSPS, f
OUT
= 60.1 and 61.1 MHz,
2 × interpolation, 320 MSPS, IOVDD = 1.8 V, 74
each tone at – 6 dBFS
Third-order two-tone
IMD3 dBc
intermodulation
f
DATA
= 100 MSPS, f
OUT
= 15.1 and 16.1 MHz,
2 × interpolation, 200 MSPS, IOVDD = 1.8 V, 84
each tone at – 6 dBFS
f
DATA
= 100 MSPS, f
OUT
= 15.6 MHz, 15.8 MHz, 16.2 MHz,
IMD Four-tone intermodulation 16.4 MHz, 4 × interpolation, 400 MSPS, IOVDD = 1.8 V, each 85 dBc
tone at – 12 dBFS
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8
V, IOUT
FS
= 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CMOS Interface
V
IH
High-level input voltage 2 3 V
V
IL
Low-level input voltage 0 0 0.8 V
I
IH
High-level input current – 40 40 A
I
IL
Low-level input current – 40 40 A
Input capacitance 5 pF
I
L
= – 100 A IOVDD – 0.2
High-level output voltage,
V
OH
V
PLLLOCK, SDO, SDIO (I/O)
I
L
= – 8 mA 0.8 × IOVDD
I
L
= 100 A 0.2
Low-level output voltage,
V
OL
V
PLLLOCK, SDO, SDIO (I/O)
I
L
= 8 mA 0.22 × IOVDD
PLL
(2)
Input data rate supported 1 160 MSPS
At 600-kHz offset, measured at
DAC output, 25-MHz 0-dBFS tone, 128
f
DATA
= 125 MSPS, 4 × interpolation
Phase noise dBc/Hz
At 6-MHz offset, measured at DAC
output, 25-MHz 0-dBFS tone, f
DATA
151
= 125 MSPS, 4 × interpolation
VCO minimum frequency PLL_rng = 00 (nominal) 120 MHz
VCO maximum frequency PLL_rng = 00 (nominal) 500 MHz
NCO
NCO clock (DAC update rate) 320 MHz
Serial Port Timing
Setup time, SDENB to rising edge
t
su(SDENB)
20 ns
of SCLK
Setup time, SDIO valid to rising
t
su(SDIO)
10 ns
edge of SCLK
Hold time, SDIO valid to rising
t
h(SDIO)
5 ns
edge of SCLK
t
SCLK
Period of SCLK 100 ns
t
SCLKH
High time of SCLK 40 ns
t
SCLKL
Low time of SCLK 40 ns
(1) Specifications subject to change without notice.
(2) See the Non-Harmonic Clock-Related Spurious Signals section for information on spurious products generated in PLL clock mode.
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