Datasheet

DAC5682Z
www.ti.com SLLS853E –AUGUST 2007–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS — AC SPECIFICATION
(1)
(continued)
Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUT
FS
= 20 mA,
4:1 transformer output termination, 50Ω doubly terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Single carrier, baseband, 2X2, PLL off, CLKIN = 983.04 MHz,
80 83
DACA and DACB on
Single carrier, IF = 180 MHz, 2X2, PLL off,
73
CLKIN = 983.04 MHz, DACA and DACB on
Adjacent channel leakage
ACLR
(2)
dBc
ratio
Four carrier, IF = 180 MHz, 2X2 CMIX, PLL off,
68
CLKIN = 983.04 MHz, DACA and DACB on
Four carrier, IF = 275 MHz, 2X2 CMIX, PLL off,
66
CLKIN = 983.04 MHz, DACA and DACB on
50-MHz offset, 1-MHz BW, Single Carrier, baseband, 2X2, PLL
93
off, CLKIN = 983.04
Noise floor
(3)
dBc
50-MHz offset, 1-MHz BW, Four Carrier, baseband, 2X2, PLL off,
85
CLKIN = 983.04.
(2) W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms
(3) Carrier power measured in 3.84 MHz BW.
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)
over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INTERFACE: D[15:0]P/N , SYNCP/N, DCLKP/N
(1)
Logic high differential
V
A,B+
175 mV
input voltage threshold
Logic low differential input
V
A,B–
–175 mV
voltage threshold
V
COM1
Input Common Mode SYNCP/N, D[15:0]P/N only 1.0 V
DCLKP/N only DVDD
V
COM2
Input Common Mode V
÷2
Z
T
Internal termination SYNCP/N, D[15:0]P/N only 85 110 135 Ω
C
L
LVDS Input capacitance 2 pF
DCLKP/N: 0 to 125MHz (see Figure 33) DLL Setup_min 1100
t
S
, t
H
DCLK to Data Disabled, CONFIG5 DLL_bypass = 1, ps
Hold_min –600
CONFIG10 = '00000000'
Positive 1000
DCLKP/N = 150 MHz
Negative –1800
Positive 800
DCLKP/N = 200 MHz
Negative –1300
Positive 600
DCLKP/N = 250 MHz
Negative –1000
Positive 450
DLL Enabled,
DCLKP/N = 300 MHz
Negative –800
t
SKEW(A),
CONFIG5
DCLK to Data Skew
(2)
ps
t
SKEW(B)
DLL_bypass = 0,
Positive 400
DCLKP/N = 350 MHz
DDR format
Negative –700
Positive 300
DCLKP/N = 400 MHz
Negative –600
Positive 300
DCLKP/N = 450 MHz
Negative –500
Positive 350
DCLKP/N = 500 MHz
Negative –300
(1) See LVDS INPUTS section for terminology.
(2) Positive skew: Clock ahead of data.
Negative skew: Data ahead of clock.
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