Datasheet

DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
ELECTRICAL CHARACTERISTICS — DC SPECIFICATION
over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, Iout
FS
= 20 mA
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 Bits
DC ACCURACY
(1)
INL Integral nonlinearity 1 LSB = IOUTFS/2
16
±4
LSB
DNL Differential nonlinearity ±2
ANALOG OUTPUT
Course gain linearity ±0.04 LSB
Offset error Mid code offset 0.01 %FSR
Gain error With external reference 1 %FSR
Gain error With internal reference 0.7 %FSR
Gain mismatch With internal reference, dual DAC –2 2 %FSR
Minimum full scale output current
(2)
2
mA
Maximum full scale output current
(2)
20
AVDD AVDD V
Output Compliance range
(3)
IOUTFS = 20 mA
–0.5V + 0.5V
Output resistance 300 kΩ
Output capacitance 5 pF
REFERENCE OUTPUT
V
ref
Reference voltage 1.14 1.2 1.26 V
Reference output current
(4)
100 nA
REFERENCE INPUT
V
EXTIO
Input voltage range 0.1 1.25 V
Input resistance 1 MΩ
CONFIG6: BiasLPF_A and BiasLPF_B = 0 95
Small signal bandwidth kHz
CONFIG6: BiasLPF_A and BiasLPF_B = 1 472
Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
ppm of
Offset drift ±1
FSR/°C
With external reference ±15
ppm of
Gain drift
FSR/°C
With internal reference ±30
Reference voltage drift ±8 ppm/°C
POWER SUPPLY
Analog supply voltage, AVDD 3.0 3.3 3.6 V
Digital supply voltage, DVDD 1.7 1.8 1.9 V
Clock supply voltage, CLKVDD 1.7 1.8 1.9 V
I/O supply voltage, IOVDD 3.0 3.3 3.6 V
I
(AVDD)
Analog supply current 133 mA
I
(DVDD)
Digital supply current 455 mA
Mode 4 (below)
I
(CLKVDD)
Clock supply current 45 mA
I
(IOVDD)
IO supply current 12 mA
(1) Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD.
(2) Nominal full-scale current, IoutFS, equals 16 × IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5682Z device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.
6 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links: DAC5682Z