Datasheet

DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
REVISION HISTORY
Changes from Revision Oct 2007 (*) to Revision A Page
• Changed from product preview to production data ............................................................................................................... 1
Changes from Revision A (Nov 2007) to Revision B Page
• Changed t
r(IOUT)
spec. output rise time 10% to 90% typical value from 2 ns to 220 ps ........................................................ 8
• Changed t
f(IOUT)
spec. output fall time 10% to 90% typical value from 2 ns to 220 ps ......................................................... 8
• Changed Z
T
spec. internal termination from 100 Ω min, 120 Ω max; to 85 Ω min, 135 Ω max ........................................... 9
• Deleted temperature deratings for f
DATA
specifications ....................................................................................................... 10
• Added DLL operating frequency range specifications ........................................................................................................ 10
• Changed In-Band SFDR vs IF, Figure 6 ............................................................................................................................. 12
• Changed C
AC
values from 0.1 to 0.01μF, Figure 37 ........................................................................................................... 37
• Changed capacitor values from 0.1 to 0.01μF, Figure 42 .................................................................................................. 40
Changes from Revision B (Apr 2008) to Revision C Page
• Changed Thermal Conductivity θ
JA
(still air) from 22 to 20 .................................................................................................. 5
• Changed θ
JC
from 7 to 0.2 .................................................................................................................................................... 5
• Changed θ
JP
from 0.2 to 3.5 ................................................................................................................................................. 5
• Changed DC Spec - Analog Output test condition from "without internal reference" ........................................................... 6
• Changed DC spec. REFERENCE INPUT, Small signal bandwidth conditions .................................................................... 6
• Changed Power Supply DVDD MIN from 1.71 to 1.7 and MAX from 2.15 to 1.9 ................................................................ 6
• Changed Power Supply CLKVDD MIN from 1.71 to 1.7 and MAX from 2.15 to 1.9 ............................................................ 6
• Added "DC tested" to PSRR spec. ....................................................................................................................................... 7
• Added Digital latency spec. .................................................................................................................................................. 8
• Added Power-up time spec ................................................................................................................................................... 8
• Added D[15:0]P/N ................................................................................................................................................................. 9
• Changed V
ITH+
spec .............................................................................................................................................................. 9
• Changed V
ITH–
spec .............................................................................................................................................................. 9
• Changed I
IH
and I
IL
spec from –40 MIN and +40 MAX to ±20 TYP .................................................................................... 10
• Changed t
(SCLK)
term to t
(SCLKL)
for Low time of SCLK ........................................................................................................ 10
• Changed Clock Input Differential voltage from 0.5V to 0.4V MIN and added footnote ...................................................... 10
• Changed last sentence of Dual-Channel Real Upconversion paragraph. .......................................................................... 33
• Added modes to Dual-Channel Real Upconversion Options .............................................................................................. 33
• Added references to CDCE62005 (3 places) ..................................................................................................................... 35
• Added explanatory paragraph for LVDS Inputs; prior to Figure 40 .................................................................................... 39
• Changed Figure 41 waveform label V
A,B
callout ................................................................................................................ 40
• Added explanatory paragraph for Figure 42. ...................................................................................................................... 40
• Changed Recommended DAC Startup Sequence ............................................................................................................. 41
• Added Multi-DAC Synchronization Procedure .................................................................................................................... 41
• Changed calculation for C2 Designing the PLL Loop Filter .............................................................................................. 46
• Added URL link to calculator file. ........................................................................................................................................ 47
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