Datasheet

DAC-A
DAC-B
Q-FIR1
CMIX1
I-FIR1
CMIX0
Q-FIR0
I-FIR0
FIFO & Demux
100
100
100
100
CLKIN/C
opt.
PLL
Loop
Filter
DLL
DAC5682ZDAC
100
FPGA
PLL
÷1÷4
ClockDivider /
Distribution
CDCM7005
100
250 MHz
1000 MHz
PLL/
DLL
VCO
N-
Divider
R-
Div
PFD
CPOUT
VCTRL_IN
TRF3761-XPLL/VCO
Loop
Filter
Div
1/2/4
DCLKP/N
SYNCP/N
D0P/N
D15P/N
375 MHzMinto 2380 MHzMax
(Dependsondividerand
“dash #” ofTRF3761)
10 MHz
OSC
Note: Forclarity, onlysignalpathsareshown.
LVDS Data Interface
Loop
Filter
VCXO
I
Q
GC5016 or GC5316 DUC,
With GC1115 CFR and/or
DPD Processor
3.3V
100
3.3V
3.3V
100
RF
Processing
Interleaved
I/QData
Sleep
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
APPLICATIONS EXAMPLES
DIGITAL INTERFACE AND CLOCKING CONSIDERATIONS FOR APPLICATION EXAMPLES
The DAC5682Z’s LVDS digital input bus can be driven by an FPGA or digital ASIC. This input signal can be
generated directly by the FPGA, or fed by a Texas Instruments Digital Up Converter (DUC) such as the GC5016
or GC5316. Optionally, a GC1115 Crest Factor Reduction (CFR) or Digital Pre-Distortion (DPD) processor may
be inserted in the digital signal chain for improving the efficiency of high-power RF amplifiers. For the details on
the DAC’s high-rate digital interface, refer to the LVDS Data Interfacing section.
A low phase noise clock for the DAC at the final sample rate can be generated by a VCXO and a Clock
Synchronizer/PLL such as the Texas Instruments CDCM7005 or CDCE62005, which can also provide other
system clocks. An optional system clocking solution can use the DAC in clock multiplying PLL mode in order to
avoid distributing a high-frequency clock at the DAC sample rate; however, the internal VCO phase noise of the
DAC in PLL mode may degrade the quality of the DAC output signal.
SINGLE COMPLEX INPUT, REAL IF OUTPUT RADIO
Refer to Figure 49 for an example Single Complex Input, Real IF Output Radio. The DAC5682Z receives an
interleaved complex I/Q baseband input data stream and increases the sample rate through interpolation by a
factor of 2 or 4. By performing digital interpolation on the input data, undesired images of the original signal can
be push out of the band of interest and more easily suppressed with analog filters. Complex mixing is available at
each stage of interpolation using the CMIX0 and CMIX1 blocks to up-convert the signal to a frequency placement
at a multiples ±Fdac/8 or ±Fdac/4. Only the real portion of the digital signal is converted by DAC-A while DAC-B
can be programmed to sleep mode for reduced power consumption. The DAC output signal would typically be
terminated with a transformer (see the Analog Current Output section). An IF filter, either LC or SAW, is used to
suppress the DAC Nyquist zone images and other spurious signals before being mixed to RF with a mixer. The
TRF3671 Frequency Synthesizer, with integrated VCO, may be used to drive the LO input of the mixer for
frequencies between 375 and 2380 MHz.
Figure 49. System Diagram of a Complex Input, Real IF Output Radio
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