Datasheet

( )
t t ´ t t
æ ö
t
ç ÷
t t t t t
è ø
2
2 1 2 3
C1 = 1 1 - C2 = R1 =
3 3 1 3 - 2
IOUT1
4 : 1
IOUT2
AVDD(3.3V)
100 W
100 W
AVDD(3.3V)
R
50
LOAD
W
IOUT1
1 : 1
IOUT2
AVDD (3.3V)
50 W
100 W
50 W
AVDD (3.3V)
R
50
LOAD
W
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
Figure 46. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer
Figure 47. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer
DESIGNING THE PLL LOOP FILTER
To minimize phase noise given for a given fDAC and M/N, the values of PLL_gain and PLL_range are selected
so that G
VCO
is minimized and within the MIN and MAX frequency for a given setting.
The external loop filter components C1, C2, and R1 are set by the G
VCO
, M/N, the loop phase margin φ
d
and the
loop bandwidth ω
d
. Except for applications where abrupt clock frequency changes require a fast PLL lock time, it
is suggested that φ
d
be set to at least 80 degrees for stable locking and suppression of the phase noise side
lobes. Phase margins of 60 degrees or less can be sensitive to board layout and decoupling details.
See Figure 48, the recommend external loop filter topology. C1, C2, and R1 are calculated by the following
equations:
(1)
46 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links: DAC5682Z