Datasheet

SDIO
SCLK
internal
digital in
IOVDD
IOGND
RESETB
SDENB
internal
digitalin
IOVDD
IOGND
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
CMOS DIGITAL INPUTS
Figure 43 shows a schematic of the equivalent CMOS digital inputs of the DAC5682Z. SDIO and SCLK have
pull-down resistors while RESETB and SDENB have pull-up resistors internal the DAC5682Z. See the
specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.
Figure 43. CMOS/TTL Digital Equivalent Input
DIGITAL SELF TEST MODE
The DAC5682Z has a Digital Self Test (SLFTST) mode to designed to enable board level testing without
requiring specific input data test patterns. The SLFTST mode is enabled via the CONFIG1 SLFTST_ena bit and
results are only valid when CONFIG3 SLFTST_err_mask bit is cleared. An internal Linear Feedback Shift
Register (LFSR) is used to generate the input test patterns for the full test cycle while a checksum result is
computed on the digital signal chain outputs. The LVDS input data bus is ignored in SLFTST mode. After the test
cycle completes, if the checksum result does not match a hardwired comparison value, the STATUS4
SLFTST_err bit is set and will remain set until cleared by writing a ‘0’ to the SLFTST_err bit. A full self test cycle
requires no more than 400,000 CLKIN/C clock cycles to complete and will automatically repeat until the
SLFTEST_ena bit is cleared.
To initiate a the Digital Self Test:
1. Provide a normal CLKIN/C input clock. (The PLL is not used in SLFTST mode)
2. Provide a RESETB pulse to perform a hardware reset on device.
3. Program the registers with the values shown in Table 10. These register values contain the settings to
properly configure the SLFTST including SLFTST_ena and SLFTST_err_mask bits
4. Provide a ‘1’ on the SYNCP/N input to initiate TXENABLE.
5. Wait at a minimum of 400,000 CLKIN/C cycles for the SLFTST to complete. Example: If CLKIN = 1GHz, then
the wait period is 400,000 × 1 / 1GHz = 400 μSec.
6. Read STATUS4 SLFTST_err bit. If set, a self test error has occurred. The SLFTST_err status may
optionally be programmed to output on the SDO pin if using the 3-bit SIF interface. See Table 10 Note (1).
7. (Optional) The SLFTST function automatically repeats until SLFTST_ena bit is cleared. To the loop the test,
write a ‘0’ to STATUS4 SLFTST_err to clear previous errors and continue at step 5 above.
8. To continue normal operating mode, provide another RESETB pulse and reprogram registers to the desired
normal settings.
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