Datasheet

DCLKP
100 W
DLL
Circuit
DAC5682Z
DCLKN
GND
V
COM2
=~ DVDD/2
0.01 Fm
Self-bias (V
BIAS
)
V
V
B
A,B
V
A
Note: AC Coupled
0.01 Fm
D[15:0]P,
SYNCP
100 W
LVDS
Receiver
DAC5682Z
D[15:0]N,
SYNCN
GND
V
COM1
=
(V
A
+V
B
)/2
V
B
V
A,B
V
A
V
A
V
B
Logical Bit
Equivalent
1.40V
1.00V
400 mV
0V
-400 mV
1
0
Example
V
A,B
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
Figure 41. LVDS Data (DxP/N, D[15:0]P/N SYNCP/N Pairs) Input Levels
Table 9. Example LVDS Data Input Levels
APPLIED VOLTAGES RESULTING RESULTING COMMON- LOGICAL BIT BINARY
DEFERENTIAL MODE VOLTAGE EQUIVALENT
VOLTAGE
V
A
V
B
V
A,B
V
COM1
1.4 V 1.0 V 400 mV 1.2 V 1
1.0 V 1.4 V –400 mV 0
1.2 V 0.8 V 400 mV 1.0 V 1
0.8 V 1.2 V –400 mV 0
Figure 42 shows the DCLKP/N LVDS clock input levels. Unlike the D[15:0]P/N and SYNCP/N LVDS pairs, the
DCLKP/N pair does not have an internal resistor and the common-mode voltage is self-biased to approximately
DVDD/2 in order to optimize the operation of the DLL circuit. For proper external termination a 100-Ω resistor
needs to be connected across the LVDS clock source lines followed by series 0.01-μF capacitors connected to
each of the DCLKP and DCLKN pairs. For best performance, the resistor and capacitors should be placed as
close as possible to these pins.
Figure 42. LVDS Clock (DCLKP/N) Input Levels
LVDS SYNCP/N Operation
The SYNCP/N LVDS input control functions as a combination of Transmit Enable (TXENABLE) and
Synchronization trigger. If SYNCP is low, the transmit chain is disabled so input data from the FIFO is ignored
while zeros are inserted into the data path. If SYNCP is raised from low to high, a synchronization event occurs
with behavior defined by individual control bits in registers CONFIG1 and CONFIG5. The SYNCP/N control is
sampled and input into the FIFO along with the other LVDS data to maintain timing alignment with the data bus.
Refer to Figure 39.
The software_sync_sel and software_sync controls in CONFIG3 provide a substitute for external SYNCP/N
control; however, since the serial interface is used no timing control is provided with respect to the DAC clock.
40 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links: DAC5682Z