Datasheet
VCO
N-
Divider
Charge
Pump
R-
Div
Status & Control
PFD
10 MHz
REF
OSC
REF_IN
CLK
DATA
STRB
CHIP_EN
PD_BUF
CPOUT
VCTRL_IN
90
0
TRF3703 AQM
DAC
DAC
LPF
Q-FIR1
CMIX1
I-FIR1
CMIX0
Q-FIR0
I-FIR0
FIFO & Demux
100
100
100
100
Control
SDIO
SDO
SDENB
SCLK
RESETB
CLKP
opt.
PLL
Loop
Filter
DLL
100
DAC5682Z DAC
PLL
Synth
TRF3761-X PLL/VCO
Loop
Filter
÷1÷4
Status &
Control
LE
DATA
CLK
PD#
RESET#
VCXO
CLKP
Loop
Filter
Div
1/2/4
Clock Divider /
Distribution
VCXO_STATUS
REF_STATUS
PLL_LOCK
LOCK_DET
CDCM7005
5V
5V
SERDES
100
DAC5682Z
Control
1.0 GHz250 MHz
1000 MHz
~ 2.1 GHz
Term
Term
Parallel to SERDES
Formatter
SERDES
SERDES
SERDES
DCLK
SYNC
D0
D15
DLL
CDCM7005
Control
TRF3761-X
Control
FPGA / ASIC
500 MHz
Toggling
Data Bit
1.0 GBPS
(DDR)
4x Clock
Multiplier
1.0 GHz
250 MHz
TX
Data Source
PA
Duplexer
Antenna
To TX
Feedback
To RX
Path
LPF
I
Q
I-Signal
Q-Signal
Freq/Phase Locked
Term
Term
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012
www.ti.com
LVDS DATA INTERFACING
Interfacing very high-speed LVDS data and clocks presents a big challenge to system designers as they have
unique constraints and are often implemented with specialized circuits to increase bandwidth. One such
specialized LVDS circuit used in many FPGAs and ASICs is a SERializer-DESerializer (SERDES) block. For
interfacing to the DAC5682Z, only the SERializer functionality of the SERDES block is required. SERDES drivers
accept lower rate parallel input data and output a serial stream using a shift register at a frequency multiple of
the data bit width. For example, a 4-bit SERDES block can accept parallel 4-bit input data at 250 MSPS and
output serial data 1000 MSPS.
External clock distribution for FPGA and ASIC SERDES drivers often have a chip-to-chip system constraint of a
limited input clock frequency compared to the desired LVDS data rate. In this case, an internal clock multiplying
PLL is often used in the FPGA or ASIC to drive the high-rate SERDES outputs. Due to this possible system
clocking constraint, the DAC5682Z accommodates a scheme where a toggling LVDS SERDES data bit can
provide a “data driven” half-rate clock (DCLK) from the data source. A DLL on-board the DAC is used to shift the
DCLK edges relative to LVDS data to maintain internal setup and hold timing.
To increase bandwidth of a single 16-bit input bus, the DAC5682Z assumes Double Data Rate (DDR) style
interfacing of data relative to the half-rate DCLK. Refer to Figure 38 and Figure 39 providing an example
implementation using FPGA-based LVDS data and clock interfaces to drive the DAC5682Z. In this example, an
assumed system constraint is that the FPGA can only receive a 250 MHz maximum input clock while the desired
DAC clock is 1000 MHz. A clock distribution chip such as the CDCM7005 or the CDCE62005 is useful in this
case to provide frequency and phase locked clocks at 250 MHz and 1000 MHz.
Figure 38. Example Direct Conversion System Diagram
From the example provided by Figure 39, driving LVDS data into the DAC using SERDES blocks requires a
parallel load of 4 consecutive data samples to shift registers. Color is used in the figure to indicate how data and
clocks flow from the FPGA to the DAC5682Z. The figure also shows the use of the SYNCP/N input, which along
with DCLK, requires 18 individual SERDES data blocks to drive the DAC’s input data FIFO that provides an
elastic buffer to the DAC5682Z digital processing chain.
38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Links: DAC5682Z