Datasheet

V
TT
R
PU
R
PD
0.01 µF
0.01 µF
100 
CLKIN
CLKINC
C
AC
Differential ECL
or (LV)PECL
Source
R
PU
and R
PD
are chosen
based on the clock driver
CLKIN
CLKINC
GND
6kW
GND
CLKVDD
CLKVDD
6kW
Note:Inputandoutputcommonmode
levelself-biasestoapproximatelyCLKVDD/2,
or0.9Vnormal.
27kW
27kW
DVDD
DVDD
GND
GND
DCLKP
DCLKN
Note:Inputandoutputcommonmode
levelself-biasestoapproximatelyDVDD/2,
or0.9Vnormal.
DAC5682Z
www.ti.com SLLS853E –AUGUST 2007–REVISED AUGUST 2012
CLOCK INPUTS
Figure 35 shows an equivalent circuit for the LVDS data input clock (DCLKP/N).
Figure 35. DCLKP/N Equivalent Input Circuit
Figure 36 shows an equivalent circuit for the DAC input clock (CLKIN/C).
Figure 36. CLKIN/C Equivalent Input Circuit
Figure 37 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
Figure 37. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source
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