Datasheet

CLKIN
CLKINC
CLKVDD (1.8V, Pin 1)
Charge
Pump
N–Divider
(1, 2, 4, 8)
PFD
F
VCO
VCO
÷2
F
PLL
M-Divider
( 1,2,4,8,16,32)
PLL Bypass
ClockMultiplyingPLL
External
Loop
Filter
Tointernal
DACclock
distribution
LPF (Pin 64)
F
VCO
/M
F
REF
F
VCO
F
REF
/N
PLL Sleep
PLL_m(4:0)
(CONFIG9)
PLL_n(2:0)
(CONFIG9)
PLL_sleep
(CONFIG6)
VCO_div2
(CONFIG11)
PLL_gain(1:0),
PLL_range(3:0)
(CONFIG11)
PLL_bypass
viaCONFIG5
PLL_LPF_reset
(CONFIG11)
F
VCO
/2
IOVDD (3.3V, Pin 9)
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
PLL CLOCK MODE
In PLL Clock Mode, the user provides an external reference clock to the CLKIN/C input pins. Refer to Figure 34.
An internal clock multiplying PLL uses the lower-rate reference clock to generate a high-rate clock for the DAC.
This function is very useful when a high-rate clock is not already available at the system level; however, the
internal VCO phase noise in PLL Clock Mode may degrade the quality of the DAC output signal when compared
to an external low jitter clock source.
The internal PLL has a type four phase-frequency detector (PFD) comparing the CLKIN/C reference clock with a
feedback clock to drive a charge pump controlling the VCO operating voltage and maintaining synchronization
between the two clocks. An external low-pass filter is required to control the loop response of the PLL. See the
Low-Pass Filter section for the filter setting calculations. This is the only mode where the LPF filter applies.
The input reference clock N-Divider is selected by CONFIG9 PLL_n(2:0) for values of ÷1, ÷2, ÷4 or ÷8. The VCO
feedback clock M-Divider is selected by CONFIG9 PLL_m(4:0) for values of ÷1, ÷2, ÷4, ÷8, ÷16 or ÷32. The
combination of M-Divider and N-Divider form the clock multiplying ratio of M/N. If the reference clock frequency is
greater than 160 MHz, use a N-Divider of ÷2, ÷4 or ÷8 to avoid exceeding the maximum PFD operating
frequency.
For DAC sample rates less than 500MHz, the phase noise of DAC clock signal can be improved by programming
the PLL for twice the desired DAC clock frequency, and setting the CONFIG11 VCO_div2 bit. If not using the
PLL, set CONFIG5 PLL_bypass and CONFIG6 PLL_sleep to reduce power consumption. In some cases, it
may be useful to reset the VCO control voltage by toggling CONFIG11 PLL_LPF_reset.
Figure 34. Functional Block Diagram for PLL
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