Datasheet

CLKINC
CLKIN
TwoClockModeShown:PLL =4XandEXTERNAL (PLL =OFF)
PLL =4X
CLKINC
CLKIN
EXTERNAL
DACCLK
(Internal)
DCLKN
DCLKP
t
SKEW(A)
t
SKEW(B)
ValidData(A) ValidData(B)
TransmitEnable/SynchronizationEvent
SYNCN
SYNCP
D[15:0]N
D[15:0]P
SingleDACMode(1X1)
DualDACMode(2X2)
A
0
A
0
A
1
B
0
A
2
A
1
A
3
B
1
A
N
A
N-2
A
N+1
B
N-2
t
S
t
H
DAC5682Z
www.ti.com SLLS853E –AUGUST 2007–REVISED AUGUST 2012
CLOCK AND DATA MODES
There are two modes of operation to drive the internal clocks on the DAC5682Z. Timing diagrams for both
modes are shown in Figure 33. EXTERNAL CLOCK MODE accepts an external full-rate clock input on the
CLKIN/CLKINC pins to drive the DACs and final logic stages while distributing an internally divided down clock
for lower speed logic such as the interpolating FIRs. PLL CLOCK MODE uses an internal clock multiplying PLL
to derive the full-rate clock from an external lower rate reference frequency on the CLKIN/CLKINC pins. In both
modes, an LVDS half-rate data clock (DCLKP/DCLKN) is provided by the user and is typically generated by a
toggling data bit to maintain LVDS data to DCLK timing alignment. LVDS data relative to DCLK is input using
Double Data Rate (DDR) switching using both rising and falling edges as shown in the both figures below. The
CONFIG10 register contains user controlled settings for the DLL to adjust for the DCLK input frequency and
various t
SKEW
timing offsets between the LVDS data and DCLK. The CDCM7005 and CDCE62005 from Texas
Instruments are recommended for providing phase aligned clocks at different frequencies for device-to-device
clock distribution and multiple DAC synchronization.
Figure 33. Clock and Data Timing Diagram
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