Datasheet

DAC5682Z

SLLS853E –AUGUST 2007–REVISED AUGUST 2012

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SERIAL INTERFACE

The serial port of the DAC5682Z is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC5682Z. It is compatible with most synchronous transfer formats and can be configured

as a 3 or 4 pin interface by SIF4 in register CONFIG5. In both configurations, SCLK is the serial interface input

clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in

and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device

with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 3 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 3. Instruction Byte of the Serial Interface

MSB LSB

Bit 7 6 5 4 3 2 1 0

Description R/W N1 N0 A4 A3 A2 A1 A0

R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from DAC5682Z and a low indicates a write operation to DAC5682Z.

[N1 : N0] Identifies the number of data bytes to be transferred per Table 5 below. Data is transferred MSB

first.

Table 4. Number of Transferred Bytes Within One

Communication Frame

N1 N0 Description

0 0 Transfer 1 Byte

0 1 Transfer 2 Bytes

1 0 Transfer 3 Bytes

1 1 Transfer 4 Bytes

[A4 : A0] Identifies the address of the register to be accessed during the read or write operation. For multi-

byte transfers, this address is the starting address. Note that the address is written to the

DAC5682Z MSB first and counts down for each byte.

Figure 27 shows the serial interface timing diagram for a DAC5682Z write operation. SCLK is the serial interface

clock input to DAC5682Z. Serial data enable SDENB is an active low input to DAC5682Z. SDIO is serial data in.

Input data to DAC5682Z is clocked on the rising edges of SCLK.

Product Folder Links: DAC5682Z