Datasheet
45
42
DAC5682Z
GND
CLKINC
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
DCLKP
DCLKN
D7P
D7N
D6P
D6N
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
DVDD
D1P
D1N
D0P
D0N
VFUSE
SDO
SDIO
SCLK
SDENB
LPF
DVDD
AVDD
AVDD
IOUTB1
IOUTB2
EXTLO
BIASJ
EXTIO
AVDD
IOUTA2
IOUTA1
AVDD
AVDD
DVDD
RESETB
D12N
D12P
D13N
D13P
D14N
D14P
DVDD
D15N
D15P
IOVDD
SYNCN
SYNCP
CLKIN
CLKVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
47
46
44
43
41
40
39
38
37
36
35
34
33
48
1
DAC5682Z
www.ti.com
SLLS853E –AUGUST 2007–REVISED AUGUST 2012
DAC5682Z
RGC PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
51, 54, 55, Analog supply voltage. (3.3V)
AVDD I
59, 62
BIASJ 57 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL
CLKIN 2 I enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides
clock for DAC up to 1GHz.
CLKINC 3 I Complementary external clock input. (See the CLKIN description)
CLKVDD 1 I Internal clock buffer supply voltage. (1.8 V)
LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 Ω
7, 11, 13,
termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative
15, 17, 19,
to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In dual-
21, 23, 27,
D[15..0]P I
channel mode, data for the A-channel is input while DCLKP is high.
29, 31, 33,
35, 37, 40,
D15P is most significant data bit (MSB) – pin 7
42
D0P is least significant data bit (LSB) – pin 42
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