Datasheet

DAC5682Z
www.ti.com SLLS853E –AUGUST 2007–REVISED AUGUST 2012
Register name: CONFIG10 – Address: 0x0A, Default = 0x00
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DLL_delay(3:0) DLL_invclk DLL_ifixed(2:0)
0 0 0 0 0 0 0 0
DLL_delay(3:0): The DCLKP/N LVDS input data clock has a DLL to automatically skew the clock to LVDS
data timing relationship, providing proper setup and hold times. DLL_delay(3:0) is used to
manually adjust the DLL delay ± from the fixed delay set by DLL_ifixed(2:0). Adjustment
amounts are approximate.
DLL_delay(3:0) Delay Adjust (degrees)
1000 50°
1001 55°
1010 60°
1011 65°
1100 70°
1101 75°
1110 80°
1111 85°
0000 90° (Default)
0001 95°
0010 100°
0011 105°
0100 110°
0101 115°
0110 120°
0111 125°
DLL_invclk: When set, used to invert an internal DLL clock to force convergence to a different solution.
This can be used in the case where the DLL delay adjustment has exceeded the limits of
its range.
DLL_ifixed(2:0): Adjusts the DLL delay line bias current. Refer to the Electrical Characteristics table. Used
in conjunction with the DLL_invclk bit to select appropriate delay range for a given DCLK
frequency:
'011' – maximum bias current and minimum delay range
'000' – mid scale bias current
'101' – minimum bias current and maximum delay range
'100' – do not use.
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