Datasheet

( )
VEXTIO
x DACA_gain + 1
R
bias
DAC5682Z
www.ti.com SLLS853E –AUGUST 2007–REVISED AUGUST 2012
Register name: CONFIG7 – Address: 0x07, Default = 0xFF
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DACA_gain(3:0) DACB_gain(3:0)
1 1 1 1 1 1 1 1
DACA_gain(3:0): Scales DACA output current in 16 equal steps.
DACB_gain(3:0): Same as above except for DACB.
Register name: CONFIG8 – Address: 0x08, Default = 0x00
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved DLL_restart Reserved
0 0 0 0 0 0 0 0
Reserved (7:3): Set to ‘00000’ for proper operation.
DLL_restart: This bit is used to restart the DLL. When this bit is set, the internal DLL loop filter is reset to
zero volts, and the DLL delay line is held at the center of its bias range. When cleared, the
DLL will acquire lock to the DCLK signal. A DLL restart is accomplished by setting this bit
with a serial interface write, and then clearing this bit with another serial interface write. Any
interruption in the DCLK signal or changes to the DLL programming in the CONFIG10
register must be followed by this DLL restart sequence. Also, when this bit is set, the
DLL_lock indicator in the STATUS0 register is cleared.
Reserved (1:0): Set to ‘00’ for proper operation
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