Datasheet

DAC5682Z

SLLS853E –AUGUST 2007–REVISED AUGUST 2012

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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SIF4 rev_bus clkdiv_sync Reserved Reserved DLL_bypass PLL_bypass Reserved

_dis

0 0 0 0 0 0 0 0

SIF4: When set, the serial interface is in 4 pin mode, otherwise it is in 3 pin mode. Refer to

SDO_func_sel (2:0) bits in CONFIG14 register for options available to output status

indicator data on the SDO pin.

rev_bus: Reverses the LVDS input data bus so that the MSB to LSB order is swapped. This

function is provided to ease board level layout and avoid wire crossovers in case the

LVDS data source output bus is mirrored with respect to the DAC’s input data bus.

clkdiv_sync_dis: Disables the clock divider sync when this bit is set.

Reserved (Bit 4): Set to 0 for proper operation.

Reserved (Bit 3): Set to 0 for proper operation.

DLL_bypass: When set, the DLL is bypassed and the LVDS data source is responsible for providing

correct setup and hold timing.

PLL_bypass: When set, the PLL is bypassed.

Reserved (Bit 0): Set to 0 for proper operation.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Unused Sleep_B Sleep_A BiasLPF_A BiasLPF_B PLL_sleep DLL_sleep

0 0 0 0 1 1 0 0

Reserved (Bit 7): Set to 0 for proper operation.

Sleep_B: When set, DACB is put into sleep mode. DACB is not automatically set into sleep mode

when configured for single DAC mode via dual_DAC bit in CONFIG2. Set this Sleep_B

bit for the lowest power configuration in single DAC mode since output is on DACA only.

Sleep_A: When set, DACA is put into sleep mode.

BiasLPF_A: Enables a 95 kHz low pass filter corner on the DACA current source bias when cleared. If

this bit is set, a 472 kHz filter corner is used.

BiasLPF_B: Enables a 95 kHz low pass filter corner on the DACB current source bias when cleared. If

this bit is set, a 472 kHz filter corner is used.

PLL_sleep: When set, the PLL is put into sleep mode.

DLL_sleep: When set, the DLL is put into sleep mode.

Product Folder Links: DAC5682Z