Datasheet

DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
DETAILED DESCRIPTION
The primary modes of operation, listed in Table 1, are selected by registers CONFIG1, CONFIG2 and CONFIG3.
Table 1. DAC5682Z Modes of Operation
LVDS Max Total
No. of FIR0, FIR1, Input Max DCLK Input Bus Max Input Data Max Signal
Mode DACs Interp. CMIX0 CMIX1 Device Data Max CLKIN Freq [DDR] Rate Rate Per Chan BW Per DAC
Name Out Factor Mode Mode Config. Mode Freq (MHz)
(1)
(MHz) (MSPS) (#Ch @ MSPS) (MHz)
(2)
1X1 1 X1 – – Single Real A 1000 500 1000 1 at 1000 500
(Bypass)
1X2 1 X2 – LP Single Real A 1000 250 500 1 at 500 200
1X2 HP 1 X2 – HP Single Real A 1000 250 500 1 at 500 200
1X4 1 X4 LP LP Single Real A 1000 125 250 1 at 250 100
1X4 LP/HP 1 X4 LP HP Single Real A 1000 125 250 1 at 250 100
1X4 HP/LP 1 X4 HP LP Single Real A 1000 125 250 1 at 250 50
1X4 HP/HP 1 X4 HP HP Single Real A 1000 125 250 1 at 250 50
2X1 2 X1 – – Dual Real A/B 500 500 1000 2 at 500 250
2X2 2 X2 – LP Dual Real A/B 1000 500 1000 2 at 500 200
2X2 HP 2 X2 – HP Dual Real A/B 1000 500 1000 2 at 500 200
2X2 CMIX 2 X2 – LP, Complex A/B 1000 500 1000 2 at 500 200
Fs/4
2X4 2 X4 LP LP Dual Real A/B 1000 250 500 2 at 250 100
2X4 LP/HP 2 X4 LP HP Dual Real A/B 1000 250 500 2 at 250 100
2X4 CMIX 2 X4 LP LP, Complex A/B 1000 250 500 2 at 250 100
Fs/4
2X4 HP/LP 2 X4 HP LP Dual Real A/B 1000 250 500 2 at 250 50
2X4 HP/HP 2 X4 HP HP Dual Real A/B 1000 250 500 2 at 250 50
(1) Also the final DAC sample rate in MSPS.
(2) Assumes a 40% passband for FIR0 and/or FIR1 filters in all modes except 1X1 and 2X1 where simple Nyquist frequency is listed.
Slightly wider bandwidths may be achievable depending on filtering requirements. Refer to FIR Filters section for more detail on filter
characteristics. Also refer to Table 7 for IF placement and upconversion considerations.
Table 2. Register Map
(MSB) (LSB)
Name Address Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 7 Bit 0
STATUS0 0x00 0x03 PLL_lock DLL_lock Unused device_ID(2:0) version(1:0)
CONFIG1 0x01 0x10 DAC_delay(1:0) Unused fir_ena SLFTST _ena FIFO_offset(2:0)
CONFIG2 0x02 0xC0 Twos_ comp dual_DAC FIR2x4x Unused CMIX1_mode(1:0) CMIX0_mode(1:0)
SLFTST_err Pattern_err
CONFIG3 0x03 0x70 DAC_offset _ena FIFO_err_ mask SwapAB_ out B_equals _A SW_sync SW_sync _sel
_mask _mask
STATUS4 0x04 0x00 Unused SLFTST_err FIFO_err Pattern_ err Unused Unused Unused Unused
PLL_
CONFIG5 0x05 0x00 SIF4 rev_bus clkdiv_ sync_dis Reserved Reserved DLL_ bypass Reserved
bypass
CONFIG6 0x06 0x0C Reserved Unused Sleep_B Sleep_A BiasLPF_A BiasLPF_B PLL_ sleep DLL_ sleep
CONFIG7 0x07 0xFF DACA_gain(3:0) DACB_gain(3:0)
CONFIG8 0x08 0x00 Reserved DLL_ restart Reserved
CONFIG9 0x09 0x00 PLL_m(4:0) PLL_n(2:0)
CONFIG10 0x0A 0x00 DLL_delay(3:0) DLL_invclk DLL_ifixed(2:0)
CONFIG11 0x0B 0x00 PLL_LPF _reset VCO_div2 PLL_gain(1:0) PLL_range(3:0)
CONFIG12 0x0C 0x00 Reserved(1:0) Offset_sync OffsetA(12:8)
CONFIG13 0x0D 0x00 OffsetA(7:0)
CONFIG14 0x0E 0x00 SDO_func_sel(2:0) OffsetB(12:8)
CONFIG15 0x0F 0x00 OffsetB(7:0)
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