Datasheet

CLKIN
CLKINC
LPF
DCLKP
CLKVDD (1.8V)
DVDD (1.8V)
VFUSE (1.8V)
GND
1.2V
Reference
EXTIO
EXTLO
BIASJ
IOUTB1
IOUTB2
16bit
DAC
Clock Multiplying
PLL 2x-32x
D0P
D0N
D15P
D15N
DCLKN
SDIO
IOVDD
(3.3V)
SYNCP
SYNCN
SDENB
RESETB
SCLK
SDO
100
100
IOUTA1
IOUTA2
16bit
DAC
Delay Lock
Loop (DLL)
FIR1 Enable FIR0Enable
FIFO Sync Disable
Sync & Control
x2 x2
x2
16
DLL Control
x2
FIR0
CM1 Mode
Mode Control
DACA_gain
DACB_gain
4
4
Delay Value
SYNC=’0->1'
(transition)
100
16
PLL Control
Clock
Distribution
FDAC
FDAC/2
PLL Bypass
2
AVDD (3.3V)
PLL Enable
16
B
A
CMIX0
[Modes = LP, HP, Fs/8, -Fs/8]
DAC Delay (0-3)
B-Offset
13
A-Offset
13
FIR1
(x2 Bypass) (x1 Bypass)
CM0 Mode
8 Sample FIFO
DDR De-interleave
TXEnable=’1'
FDAC/4
SW_Sync
22
47t 76dB HBF 47t 76dB HBF
47t 76dB HBF47t 76dB HBF
CMIX1
[Modes = LP, HP, Fs/4, -Fs/4]
16
Sync Disable
DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
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