Datasheet

DAC5682Z
SLLS853E –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)
over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format,
250
DCLKP frequency: <125 MHz
Input
f
DATA
MSPS
data rate supported
DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format,
250 1000
DCLKP frequency: 125 to 500 MHz
CONFIG10 = '11001101' = 0xCD 125 150
DLL Enabled,
CONFIG10 = '11001110' = 0xCE 150 175
DLL Operating Frequency CONFIG5
CONFIG10 = '11001111' = 0xCF 175 200 MHz
(DCLKP/N Frequency) DLL_bypass = 0,
CONFIG10 = '11001000' = 0xC8 200 325
DDR format
CONFIG10 = '11000000' = 0xC0 325 500
CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB
V
IH
High-level input voltage 2 3 V
V
IL
Low-level input voltage 0 0 0.8 V
I
IH
High-level input current ±20 μA
I
IL
Low-level input current ±20 μA
CI CMOS Input capacitance 5 pF
IOVDD
I
load
= –100 μA V
–0.2
V
OH
SDO, SDIO
0.8
I
load
= –2mA V
x IOVDD
I
load
= 100 μA 0.2 V
V
OL
SDO, SDIO
I
load
= 2 mA 0.5 V
Setup time, SDENB to
t
s(SDENB)
20 ns
rising edge of SCLK
Setup time, SDIO valid to
t
s(SDIO)
10 ns
rising edge of SCLK
Hold time, SDIO valid to
t
h(SDIO)
5 ns
rising edge of SCLK
t
(SCLK)
Period of SCLK 100 ns
t
(SCLKH)
High time of SCLK 40 ns
t
(SCLKL)
Low time of SCLK 40 ns
Data output delay after
t
d(Data)
10 ns
falling edge of SCLK
Minimum RESETB pulse
t
RESET
25 ns
width
CLOCK INPUT (CLKIN/CLKINC)
Duty cycle 50%
Differential voltage
(3)
0.4 1 V
CLKIN/CLKINC input CLKVDD
V
common mode ÷2
PHASE LOCKED LOOP
DAC output at 600 kHz offset, 100 MHz, 0-dBFS tone,
2X4, f
DATA
= 250 MSPS, CLKIN/C = 250 MHz,
–125
PLL_m = '00111', PLL_n = '001', VCO_div2 = 0,
PLL_range = '1111', PLL_gain = '00'
Phase noise dBc/ Hz
DAC output at 6 MHz offset, 100 MHz, 0-dBFS tone,
2X4, f
DATA
= 250 MSPS, CLKIN/C = 250 MHz,
–146
PLL_m = '00111', PLL_n = '001', VCO_div2 = 0,
PLL_range = '1111', PLL_gain = '00'
(3) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.
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