DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC) Check for Samples: DAC5682Z FEATURES DESCRIPTION • • • The DAC5682Z is a dual-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x interpolation filters, on-board clock multiplier and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk and PLL phase noise performance.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. (3.3V) AVDD (1.8V) VFUSE (1.8V) DVDD LPF (1.
DAC5682Z www.ti.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. D[15..0]N 8, 12, 14, 16, 18, 20, 22, 24, 28, 30, 32, 34, 36, 38, 41, 43 I/O DESCRIPTION LVDS negative input data bits 0 through 15. (See D[15:0]P description above) D15N is most significant data bit (MSB) – pin 8 D0N is least significant data bit (LSB) – pin 43 I 25 I LVDS positive input clock.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) DVDD Supply voltage range (1) (2) VALUE UNIT –0.5 to 2.3 V VFUSE (2) –0.5 to 2.3 V CLKVDD (2) –0.5 to 2.3 V –0.5 to 4 V (2) –0.5 to 4 V AVDD to DVDD –2 to 2.6 V –0.5 to 0.5 V AVDD (2) IOVDD CLKVDD to DVDD IOVDD to AVDD –0.5 to 0.5 V –0.5 to DVDD + 0.5 V –0.3 to 2.1 V –0.5 to CLKVDD + 0.5 V –0.5 to IOVDD + 0.5 V –0.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — DC SPECIFICATION over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS — DC SPECIFICATION (continued) over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER I(AVDD) Sleep mode, AVDD supply current I(DVDD) Sleep mode, DVDD supply current I(CLKVDD) Sleep mode, CLKVDD supply current I(IOVDD) Sleep mode, IOVDD supply current AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — AC SPECIFICATION (1) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT fCLK Maximum output update rate ts(DAC) Output settling time to 0.1% tpd 1000 Transition: Code 0x0000 to 0xFFFF MSPS 10.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS — AC SPECIFICATION(1) (continued) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS Single carrier, baseband, 2X2, PLL off, CLKIN = 983.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS Figure 1. Integral Nonlinearity Figure 2.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) 95 Fdata = 250 MSPS, FIN = -80 MHz Complex, (-80+250=170) IF = 170 MHz, CMIX, FS/4 x4 Interpolation PLL Off 0 -10 Power - dBm -20 -30 -40 -50 -60 -70 -80 0 50 SFDR - Spurious Free Dynamic Range - dBc 10 Fdata = 250 MSPS, x4 Interpolation, PLL Off 90 85 80 75 70 0 dBFS 65 60 0 100 150 200 250 300 350 400 450 500 f - Frequency - MHz 10 20 30 40 IF - Intermediate Frequency - MHz Figure 5.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 85 80 89.5 and 90.5 MHz (CMIX Off) Fdata = 500 MSPS, -10 F = 40 ± 0.5 MHz Real, IN IF = 40 MHz, -20 x2 Interpolation PLL Off 75 -30 65 Shift to 340 MHz (FS/8 On) 60 55 Shift to 215 MHz (FS/4 On) -25 -20 -15 -10 Amplitude - dBFS -5 -40 -50 -60 -70 Fdata = 250 MSPS Fin = 90 MHz ±0.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) -20 -30 -40 -20 Carrier Power: -7.60 dBm, ACLR (5 MHz): 80.66 dB, ACLR (10 MHz): 82.61 dB, Fdata = 245.76 MSPS, IF = 61.44 MHz, x4 Interpolation PLL Off -30 -40 -50 Power - dBm -50 Power - dBm Carrier Power: -7.60 dBm, ACLR (5 MHz): 77.49 dB, ACLR (10 MHz): 82.45 dB, Fdata = 245.76 MSPS, IF = 61.44 MHz, x4 Interpolation PLL On -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 48.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) -30 -40 Power - dBm -50 -20 Carrier Power: -8.99 dBm, ACLR (5 MHz): 68.22 dB, ACLR (10 MHz): 74.15 dB, Fdata = 245.76 MSPS, IF = Baseband, x4 Interpolation CMIX PLL Off Fdata = 245.76 MSPS, -40 IF = Baseband, x4 Interpolation CMIX PLL On -50 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 233 238 243 248 f - Frequency - MHz 253 -120 233 258 Figure 17.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) -20 Carrier Power: -15.85 dBm, -20 Carrier Power: -15.85 dBm, -30 -40 ACLR (5 MHz): 69.66 dB, ACLR (10 MHz): 70.65 dB, Fdata = 491.52 MSPS, IF = 184.32 MHz, x2 Interpolation PLL Off ACLR (5 MHz): 65.85 dB, -30 ACLR (10 MHz): 69.60 dB, Fdata = 491.52 MSPS, IF = 184.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TEST METHODOLOGY Typical AC specifications were characterized with the DAC5682ZEVM using the test configuration shown in Figure 25. A sinusoidal master clock frequency is generated by an HP8665B signal generator and into a splitter. One output drives an Agilent 8133A pulse generator, and the other drives the CDCM7005 clock driver.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Offset Error: Defined as the percentage error (in FSR%) for the ratio of the differential output current (IOUT1–IOUT2) and the mid-scale output current.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION The primary modes of operation, listed in Table 1, are selected by registers CONFIG1, CONFIG2 and CONFIG3. Table 1. DAC5682Z Modes of Operation Device Config.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Register name: STATUS0 – Address: 0x00, Default = 0x03 Bit 7 Bit 6 Bit 5 PLL_lock 0 DLL_lock 0 Unused 0 Bit 4 Bit 3 0 device_ID(2:0) 0 Bit 2 Bit 1 Bit 0 version(1:0) 0 1 1 PLL_lock: Asserted when the internal PLL is locked. (Read Only) DLL_lock: Asserted when the internal DLL is locked.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG2 – Address: 0x02, Default = 0xC0 Bit 7 Bit 6 Bit 5 Bit 4 Twos_comp 1 dual_DAC 1 FIR2x4x 0 Unused 0 Bit 3 Bit 2 CMIX1_mode(1:0) 0 0 Bit 1 Bit 0 CMIX0_mode(1:0) 0 0 Twos_comp: When set (default) the input data format is expected to be 2’s complement, otherwise offset binary format is expected. dual_DAC: Selects between dual DAC mode (default) and single DAC mode.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG3 – Address: 0x03, Default = 0x70 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC_offset _ena 0 SLFTST_err _mask FIFO_err_ mask Pattern_err_ mask SwapAB_out B_equals_A SW_sync SW_sync_sel 1 1 1 0 0 0 0 DAC_offset_ena: When set, the values of OffsetA(12:0) and OffsetB(12:0) in CONFIG12 through CONFIG15 registers are summed into the DAC-A and DAC-B data paths.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG5 – Address: 0x05, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIF4 rev_bus Reserved Reserved DLL_bypass PLL_bypass Reserved 0 0 clkdiv_sync _dis 0 0 0 0 0 0 SIF4: When set, the serial interface is in 4 pin mode, otherwise it is in 3 pin mode. Refer to SDO_func_sel (2:0) bits in CONFIG14 register for options available to output status indicator data on the SDO pin.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG7 – Address: 0x07, Default = 0xFF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DACA_gain(3:0) 1 1 Bit 1 Bit 0 DACB_gain(3:0) 1 1 1 DACA_gain(3:0): Scales DACA output current in 16 equal steps. VEXTIO x (DACA_gain + 1) Rbias DACB_gain(3:0): Same as above except for DACB.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG9 – Address: 0x09, Default = 0x00 Bit 7 0 Bit 6 Bit 5 0 PLL_m(4:0) 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 0 PLL_n(2:0) 0 0 PLL_m: M portion of the M/N divider of the PLL thermometer encoded: PLL_m(4:0) M value 00000 1 00001 2 00011 4 00111 8 01111 16 11111 32 All other values Invalid PLL_n: N portion of the M/N divider of the PLL thermometer encoded.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG10 – Address: 0x0A, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 DLL_invclk 0 DLL_delay(3:0) 0 DLL_delay(3:0): 0 0 Bit 2 Bit 1 Bit 0 0 DLL_ifixed(2:0) 0 0 The DCLKP/N LVDS input data clock has a DLL to automatically skew the clock to LVDS data timing relationship, providing proper setup and hold times.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG11 – Address: 0x0B, Default = 0x00 Bit 7 Bit 6 PLL_LPF_ reset 0 VCO_div2 0 Bit 5 Bit 4 Bit 3 PLL_gain(1:0) 0 0 0 Bit 2 Bit 1 PLL_range(3:0) 0 0 Bit 0 0 PLL_LPF_reset: When a logic high, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the process is fast, the supplies are higher than nominal, etc.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG14 – Address: 0x0E, Default = 0x00 Bit 7 Bit 6 0 SDO_func_sel(2:0) 0 SDO_func_sel(2:0): OffsetB(12:8): Bit 5 Bit 4 0 0 Bit 3 Bit 2 Bit 1 Bit 0 0 OffsetB(12:8) 0 0 0 Selects the signal for output on the SDO pin. When using the 3 pin serial interface mode, this allows the user to multiplex several status indicators onto the SDO pin.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com SERIAL INTERFACE The serial port of the DAC5682Z is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC5682Z. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by SIF4 in register CONFIG5.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Instruction Cycle Data Transfer Cycle (s) SDENB SCLK SDIO r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 tS (SDENB) D5 D4 D3 D2 D1 D0 tSCLK SDENB SCLK SDIO tSCLKL th (SDIO) tSCLKH tS (SDIO) Figure 27. Serial Interface Write Timing Diagram Figure 28 shows the serial interface timing diagram for a DAC5682Z read operation. SCLK is the serial interface clock input to DAC5682Z. Serial data enable SDENB is an active low input to DAC5682Z.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com FIR FILTERS Figure 29 shows the magnitude spectrum response for the identical 47-tap FIR0 and FIR1 filters. The transition band is from 0.4 to 0.6 × FIN (the input data rate for the FIR filter) with <0.002 dB of pass-band ripple and approximately 76dB of stop-band attenuation. Figure 30 shows the region from 0.35 to 0.45 × FIN – up to 0.44x FIN there is less than 0.4 dB attenuation.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Table 5.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Table 7. CMIX0 Mixer Sequences Mode CMIX0_mode(1) CMIX0_mode(0) MIXING SEQUENCE Normal (Low Pass, No Mixing) 0 0 FIR0A = { +A, +A , +A, +A } FIR0B = { +B, +B , +B, +B } High Pass 0 1 FIR0A = { +A, –A , +A, –A } FIR0B = { +B, –B , +B, –B } +FDAC /8 (+Fs/4) 1 0 FIR0A = { +A, –B , –A, +B } FIR0B = { +B, +A , –B, –A } –FDAC /8 (–Fs/4) 1 1 FIR0A = { +A, +B , –A, –B } FIR0B = { +B, –A , –B, +A } Table 8.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 CLOCK AND DATA MODES There are two modes of operation to drive the internal clocks on the DAC5682Z. Timing diagrams for both modes are shown in Figure 33. EXTERNAL CLOCK MODE accepts an external full-rate clock input on the CLKIN/CLKINC pins to drive the DACs and final logic stages while distributing an internally divided down clock for lower speed logic such as the interpolating FIRs.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com PLL CLOCK MODE In PLL Clock Mode, the user provides an external reference clock to the CLKIN/C input pins. Refer to Figure 34. An internal clock multiplying PLL uses the lower-rate reference clock to generate a high-rate clock for the DAC.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 CLOCK INPUTS Figure 35 shows an equivalent circuit for the LVDS data input clock (DCLKP/N). 27 kW DVDD DCLKP Note: Input and output common mode level self-biases to approximately DVDD/2, or 0.9 V normal. DVDD GND DCLKN GND 27 kW Figure 35. DCLKP/N Equivalent Input Circuit Figure 36 shows an equivalent circuit for the DAC input clock (CLKIN/C).
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com LVDS DATA INTERFACING Interfacing very high-speed LVDS data and clocks presents a big challenge to system designers as they have unique constraints and are often implemented with specialized circuits to increase bandwidth. One such specialized LVDS circuit used in many FPGAs and ASICs is a SERializer-DESerializer (SERDES) block. For interfacing to the DAC5682Z, only the SERializer functionality of the SERDES block is required.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 4x Clock Multiplier PLL Ref CLK Gen & Sync 250MHz Clock 4b SERDES (CLKOUT) 4 4b SERDES (SYNC) LVDS 4b SERDES (bit 15) LVDS 1,0,1,0...
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Example DAC5682Z D[15:0]P, SYNCP VCOM1 = (VA +VB )/2 LVDS Receiver 100 W VA,B VA VA 1.40 V VB 1.00 V 400 mV VA,B 0V D[15:0]N, SYNCN VB -400 mV GND 1 Logical Bit Equivalent 0 Figure 41. LVDS Data (DxP/N, D[15:0]P/N SYNCP/N Pairs) Input Levels Table 9. Example LVDS Data Input Levels APPLIED VOLTAGES RESULTING DEFERENTIAL VOLTAGE RESULTING COMMONMODE VOLTAGE VA VB VA,B VCOM1 1.4 V 1.0 V 400 mV 1.2 V 1.0 V 1.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 DLL OPERATION The DAC5682Z provides a digital Delay Lock Loop (DLL) to skew the LVDS data clock (DCLK) relative to the data bits, D[15:0] and SYNC, in order to maintain proper setup and hold timing. Since the DLL operates closedloop, it requires a stable DCLK to maintain delay lock. Refer to the description of DLL_ifixed(2:0) and DLL_delay(3:0) control bits in the CONFIG10 register.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com CMOS DIGITAL INPUTS Figure 43 shows a schematic of the equivalent CMOS digital inputs of the DAC5682Z. SDIO and SCLK have pull-down resistors while RESETB and SDENB have pull-up resistors internal the DAC5682Z. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ. IOVDD IOVDD internal digital in SDIO SCLK internal digital in RESETB SDENB IOGND IOGND Figure 43.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Table 10.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output current flow in each pin driving a resistive load can be expressed as: IOUT1 = IOUTFS × (65536 – CODE) / 65536 IOUT2 = IOUTFS × CODE / 65536 where CODE is the decimal representation of the DAC data input word.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 ANALOG CURRENT OUTPUTS Figure 45 shows a simplified schematic of the current source array output with corresponding switches in a current sink configuration. Differential switches direct the current into either the positive output node, IOUT1, or its complement, IOUT2, then through the individual NMOS current sources.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com AVDD (3.3 V) 50 W 1:1 IOUT1 RLOAD 100 W 50 W IOUT2 50 W AVDD (3.3 V) Figure 46. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer AVDD (3.3 V) 100 W 4:1 IOUT1 RLOAD 50 W IOUT2 100 W AVDD (3.3 V) Figure 47.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 where, t1 = K dK VCO w2 d (tan Φd + sec Φd ) t2 = 1 wd (tan Φd + sec Φd ) t3 = tan Φd + sec Φd wd (2) charge pump current: iqp = 1 mA vco gain: KVCO = 2π × GVCO rad/V PFD Frequency: ωd ≤160 MHz phase detector gain: Kd = iqp ÷ (2 × π × M) A/rad An Excel spreadsheet is available from Texas Instruments for automatically calculating the values for C1, R1 and C2 in the Tools & Software section of the DAC5682Z webpage; http://focus.ti.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com APPLICATIONS EXAMPLES DIGITAL INTERFACE AND CLOCKING CONSIDERATIONS FOR APPLICATION EXAMPLES The DAC5682Z’s LVDS digital input bus can be driven by an FPGA or digital ASIC. This input signal can be generated directly by the FPGA, or fed by a Texas Instruments Digital Up Converter (DUC) such as the GC5016 or GC5316.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 APPLICATIONS EXAMPLES (continued) DUAL CHANNEL REAL IF OUTPUT RADIO Refer to Figure 50 for an example Dual Channel Real IF Output Radio. The DAC5682Z receives an interleaved A/B input data stream and increases the sample rate through interpolation by a factor of 2 or 4.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com APPLICATIONS EXAMPLES (continued) RF(t) = I(t)cos(ωc + ωLO)t – Q(t)sin(ωc + ωLO)t (5) (5) Flexibility is provided to the user by allowing for the selection of negative CMIX mixing sequences to produce a lower-sideband upconversion. Note that the process of complex mixing translates the signal frequency from 0 Hz means that the analog quadrature modulator IQ imbalance produces a sideband that falls outside the signal of interest.
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 APPLICATIONS EXAMPLES (continued) HIGH-SPEED ARBITRARY WAVEFORM GENERATOR The 1GSPS bandwidth input data bus combined with the 16-bit DAC resolution of the DAC5682Z allows wideband signal generation for test and measurement applications. In this case, interpolation is not desired by the FPGA-based waveform generator as it can make use of the full Nyquist bandwidth of up to 500MHz.
DAC5682Z SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Revision Oct 2007 (*) to Revision A • Page Changed from product preview to production data ............................................................................................................... 1 Changes from Revision A (Nov 2007) to Revision B Page • Changed tr(IOUT) spec. output rise time 10% to 90% typical value from 2 ns to 220 ps ........................................................
DAC5682Z www.ti.com SLLS853E – AUGUST 2007 – REVISED AUGUST 2012 Changes from Revision C (June 2009) to Revision D Page • Changed CONFIG5 Bit4 from "FIFO_ sync_dis" to "Reserved" in Register Map .............................................................. 20 • Changed CONFIG6 Bit 7 from "Hold_ sync_dis" to "Reserved" in Register Map .............................................................. 20 • Deleted - unless-----CONFIG5 register. in FIFO_offset(2:0): on page 21 ...........................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC5682ZIRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 DAC5682ZIRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5682ZIRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC5682ZIRGCT VQFN RGC 64 250 336.6 336.6 28.
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