Datasheet
4.6 Clock Configuration
4.6.1 Buffer Mode
4.6.2 PLL Mode
4.7 Output Configurations
4.7.1 DAC Outputs
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DAC5681/81Z/82z EVM Hardware Description
Table 3. Input Connector (continued)
Pin Description Pin Description
67 D12N 121 D4N
71 D11P 125 D3P
73 D11N 127 D3N
77 D10P 131 D2P
79 D10N 133 D2N
83 D9P 137 D1P
85 D9N 139 D1N
89 D8P 143 D0P
91 D8N 145 D0N
95 DCLKP 155 SYNCP
97 DCLKN 157 SYNCN
Synchronizing Positive LVDS 161,162,163,164,165,166,167,16
96 GND
output clock 8,169,170,171,172
Synchronizing Negative LVDS
98 All others Unused
output clock
The CDCM7005 requires a VCXO or external clock source to derive its output clock signals.
The DAC5681/81z/82z EVM does not come populated with a VCXO and requires an external sine wave
source with a 1-Vrms, 0-V offset on SMA J6. Under this setup, the CDCM7005 operates as a buffer. To
select this mode, the following changes need to be made:
1. JP13 and JP14 need to be set in position 2-3.
2. If a VCXO is installed, it is recommended to disable it by removing jumper JP19.
A VCXO can be installed in U6 to operate the CDCM7005 as a PLL. The following changes need to be
made:
1. JP13 and JP14 need to be in the 1-2 position.
2. Install jumper JP19.
3. A frequency reference (internal or external) needs to be provided.
The DAC5681 and DAC5681z options are configured such that the single DAC output drives a a doubly
terminated 50- Ω cable using a 4:1 impedance ratio transformer with the center tap of the transformer
connected to +3.3 V. The output signal is found at SMA connector J3.
The DAC5682z EVM option has a resistor network that can be configured such that the DAC outputs are
routed to the TRF3703 for an RF measurement or routed to the transformer path for a DAC measurement.
The default setup on the board is for RF output.
To configure the DAC5682z EVM to evaluate the DAC outputs, the following changes need to be done to
the board:
1. R137, R153, R155 and R156 need to be uninstalled
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 9
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