Datasheet

3.1.2 CDCM7005
3.1.3 TRF3703
4 DAC5681/81Z/82z EVM Hardware Description
4.1 Jumper Settings
www.ti.com DAC5681/81Z/82z EVM Hardware Description
The DAC5681and DAC5681z are single-channel devices while the DAC5682z supports two-channels. The
DAC5681z and DAC5682z include 2x/4x interpolation filters and on-board clock multiplier with superior
phase noise performance. Each interpolation FIR is configurable in either Low-Pass or High-Pass mode,
allowing selection of a higher order output spectral image.
The DAC5682z is the only member of the family that allows a complex output. An optional Fs/4 coarse
mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces a
complex Hilbert Transform pair. An external RF quadrature modulator then performs the final single
sideband up-conversion.
The CDCM7005 is a high-performance, low-phase noise and low-skew clock synchronizer that
synchronizes a VCXO (voltage-controlled crystal oscillator) or VCO (voltage-controlled oscillator)
frequency to a reference clock. The CDCM7005 is used to generate and synchronize the clock outputs to
the system. The device has five outputs which can be configured to LVPECL or LVCMOS levels and can
be divided down by 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a
90 ° phase shift.
The TRF3703 is a very-low-noise direct quadrature modulator, capable of converting complex modulated
signals from baseband or IF directly up to RF-based on the LO frequency.
The DAC5681/81z/82z EVM can be set up in a variety of configurations to accommodate a specific mode
of operation. Before starting evaluation, the user should decide on the configuration and make the
appropriate connections or changes. The demonstration board comes with the following factory-set
configuration:
• No VCXO installed. CDCM7005 in buffer mode which requires an input single-ended clock signal to
SMA connector J6.
• On the DAC5682z EVM outputs are set by default to drive the TRF3703. The DAC5681 and
DAC5681z output is connected to J3.
• The converter is set to operate with internal reference. Jumper JP8 EXTLO is installed between pins 2
and 3.
• Full-scale output current set to 20mA through RBIAS resistor R18.
The DAC5681/81z/82z EVM has onboard jumpers that allow the user to modify the board configuration.
Table 1 explains the functionality of the jumpers.
Table 1. Jumper List
Jumper Label Function Condition Default
JP8 EXTLO Internal (GND) or external (3.3V) voltage reference GND Pin 2-3
JP10 VFUSE Factory use only. Connect to 1.8VDD for normal operation. 1.8 VDD Pin 1-2
JP12 CDC_PD Low active power down of CDCM7005 3.3 VCLK Pin 1-2
JP13 VCXOB Choose internal VCXO or external VCXO INB External VCXO Pin 2-3
JP14 VCXO_P Choose internal VCXO or external VCXO positive input External VCXO Pin 2-3
JP15 VCXO_N Choose CDCM7005 or external VBB CDCM7005 Pin 1-2
JP16 REF_CLK Choose internal 10-MHz ref or external ref Internal Ref Pin 2-3
JP17 +3.3V_IN Main or TP3 3.3 voltage source for CDCM7005 and USB Main Pin 1-2
JP19 +3.3VCLK VCXO power down 3.3 VCLK Pin 1-2
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 7
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