Datasheet

5.4 CDCM7005 Register Configuration

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DAC5681/81z/82z EVM Software

Table 7. DAC Register Configuration Software Functionality (continued)

Input

Subarea Name Description of Functionality (GUI Setting)

Output

Selects the synchronization signal source. If soft sync is selected the software sync control is used

sync source Input/Output

as the only synchronization input and the LVDS external SYNC input pins ( hard sync) are ignored.

Substitute for the LVDS external SYNC input pins for both synchronization and transmit enable

software sync Input/Output

control.

hold sync Input/Output Enables the sync to the FIFO output HOLD block.

clk div sync Input/Output Enables the clock divider sync.

FIFO sync Input/Output Enables the FIFO offset sync.

self test Input/Output Enables a Digital Self Test (SLFTST) of the core logic.

FA002 Input/Output Keep disabled. Used only for factory test purposes.

Fuse A Input/Output Keep disabled. Used only for factory test purposes.

Fuse B Input/Output Keep disabled. Used only for factory test purposes.

ATEST Input/Output Keep disabled. Used only for factory test purposes.

SEND/SAVE Button Settings (8)

Send All Input Writes all registers to the DAC device.

Reads all registers from the DAC device. It is rarely necessary to use this as the registers are read

Read All Input

every time a DAC control changes.

Loads a DAC register configuration from a text file. Files need to consist of a single column with the