Datasheet

DAC5681/81z/82z EVM Software www.ti.com
Table 7. DAC Register Configuration Software Functionality (continued)
Input
Subarea Name Description of Functionality (GUI Setting)
Output
DLL fixed current Adjusts the DLL delay line bias current. Used in conjunction with the DLL inv clock to select
Input/Output
delay (ps/ µ A) appropriate delay range for a given DCLK frequency
Inverts the internal DLL clock to force convergence to a different solution. Used when the DLL delay
DLL inv clock Input/Output
adjustment has exceeded the limits of its range.
Input Settings (3)
format Input/Output Select 2’s complement or offset binary format.
reverse bus Input/Output Reverses the LVDS input data bus so that the MSB to LSB order is swapped ( enabled)
swap data Input/Output A/B data paths are swapped prior to routing to the DACA and DACB outputs ( enabled)
same data Input/Output Data routed to DACA is also routed to DACB ( enabled)
Sets the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to +3 positions
FIFO offset Input/Output
upon SYNC. Default offset is 0 and is updated upon each sync event.
Digital Settings (4)
digital logic Input/Output Uses the interpolation filters ( enabled)
interpolation Input/Output Selects the interpolation rate.
Determines the mode of FIR0 and CMIX0 blocks. Since CMIX0 is located between FIR0 and FIR1,
CM0 mode Input/Output
its output is half-rate. Settings apply to both A and B channels.
CM1 mode Input/Output Determines the mode of FIR1 and final CMIX1 blocks. Settings apply to both A and B channels.
DAC data delay adjustment (0–3 periods of the DAC clock). Used to adjust system level output
digital delay Input/Output
timing. The same delay is applied to both DACA and DACB data paths.
Changes the number of buffers that the input clock goes through. This allows some adjustment of
clock delay Input/Output
the setup/hold of the handoff between the receivers and the digital section.
DAC Settings (5)
DAC mode Input/Output Selects dual DAC mode or single DAC mode. Used to select input interleaved data ( dual DAC).
DACA Sleep Input/Output DACA is put into sleep mode ( selected)
DACB is put into sleep mode ( selected). DACB is not automatically set into sleep mode when
DACB Sleep Input/Output configured for single DAC mode. Use this control with single DAC mode to get the lowest power
configuration for DACA output only.
DACA Gain Input/Output Scales the DACA output current in 16 equal steps.
DACB Gain Input/Output Scales the DACB output current in 16 equal steps.
Offset A and Offset B values are summed into the DACA and DACB data paths ( enabled). Provides
Offset Input/Output
a system-level offset adjustment capability that is independent of the input data.
Transfers the Offset A and Offset B values to the registers used in the DACA and DACB offset
offset sync Input/Output
calculations. This control is enabled automatically for any change in the Offset A or Offset B values.
Offset A Input/Output Offset adjustment value for the A data path.
Offset B Input/Output Offset adjustment value for the B data path.
95 kHz low pass filter corner on the DACA current source bias ( enabled). Uses a 472 Hz filter
DAC A LPF Input/Output
corner ( disabled).
95 kHz low pass filter corner on the DACB current source bias ( enabled). Uses a 472 Hz filter
DAC B LPF Input/Output
corner ( disabled).
Error Settings (6)
SLFST Error Input/Output Masks out SLFTST Errors.
FIFO Error Input/Output Masks out FIFO Errors.
Setup/Hold Error Input/Output Masks out Setup/Hold Errors.
SLFST error reset Input/Output Asserted when the Digital Self Test (SLFTST) fails. Clear to reset a SLFST error.
Asserted when the FIFO pointers overrun each other, causing a sample to be missed. Clear to reset
FIFO error reset Input/Output
a FIFO error.
Any received data pattern other than 0xAAAA or 0x5555 causes this bit to be set. Clear to reset a
Setup/Hold error reset Input/Output
Setup/Hold error.
SDO Input/Output Selects the signal polarity on the SDO pin ( normal or inverted)
SYNC Settings (7)
serial interface Input/Output Selects 3-pin or 4-pin serial interface mode.
16 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008
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