Datasheet

5.3 DAC Register Configuration and Block Diagram
www.ti.com DAC5681/81z/82z EVM Software
Figure 10. DAC Block Diagram and Register Configuration Settings
Table 7. DAC Register Configuration Software Functionality
Input
Subarea Name Description of Functionality (GUI Setting)
Output
PLL Settings (1)
PLL Input/Output Phased-locked Loop (PLL) is bypassed ( disabled)
PLL Sleep Input/Output PLL is put into sleep mode ( selected)
PLL Lock Output Internal PLL is locked ( Green)
PLL loop filter is pulled down to 0V ( set).
PLL Reset Input/Output
Toggle to restart the PLL if an over-speed lock-up occurs.
PLL clock output is one-half the PLL VCO frequency ( 2x).
VCO Frequency Input/Output Runs the VCO at twice the needed clock frequency to reduce phase noise for lower input clock
rates.
PLL Gain (MHz/V) Input/Output Adjust the PLL Voltage Controlled Oscillator (VCO) gain.
PLL Range (MHz) Input/Output Sets the PLL VCO frequency range.
M value Input/Output M portion of the M/N divider of the PLL.
N portion of the M/N divider of the PLL. This value should be chosen to divide down the input CLK
IN
N value Input/Output
to maintain a maximum PFD of 160 MHz.
DLL Settings (2)
Delay lock loop (DLL) is bypassed and LVDS data source provides correct setup and hold timing
DLL Input/Output
( disabled)
DLL Sleep Input/Output DLL is put into sleep mode ( selected)
DLL is restarted automatically when DLL settings change, so there is no need to press the DLL
Auto-DLL Input
restart control ( selected).
DLL Lock Output Internal DLL is locked ( Green)
DLL restart Input/Output Restarts the DLL manually
DLL Delay (deg.) Input/Output Manually adjust the DLL delay ± from the DLL fixed current delay.
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 15
Submit Documentation Feedback