Datasheet

f − Frequency − MHz
Power − dBm
−120
−100
−80
−60
−40
−20
7.6 10.1 12.6 15.1 17.6 20.1 22.6
f
data
= 122.88 MSPS
IF = 15.36 MHz
ACLR = 77.16 dB
Dual Bus Mode
G015
f − Frequency − MHz
Power − dBm
−120
−100
−80
−60
−40
−20
23.0 25.5 28.0 30.5 33.0 35.5 38.0
f
data
= 122.88 MSPS
IF = 30.72 MHz
ACLR = 72.7 dB
Dual Bus Mode
G016
DA[13:0]
DB[13:0]
SLEEP
CLKA/B
WRTA/B
Internal
DigitalIn
DVDD
400W
100kW
DGND
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010 www.ti.com
TYPICAL CHARACTERISTICS (continued)
POWER POWER
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
Digital Inputs and Timing
Digital Inputs
The data input ports of the DAC5672 accept a standard positive coding with data bits DA13 and DB13 being the
most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best
performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may
vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their
specified limits.
All digital inputs of the DAC5672 are CMOS compatible. Figure 17 and Figure 18 show schematics of the
equivalent CMOS digital inputs of the DAC5672. The pullup and pulldown circuitry is approximately equivalent to
100kΩ. The 14-bit digital data input follows the offset positive binary coding scheme. The DAC5672 is designed
to operate with a digital supply (DVDD) of 3 V to 3.6 V.
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5672