Datasheet

Valid Data
D[11:0]
t
su
t
h
t
lat
t
pd
t
settle
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
IOUT
or
IOUT
DAC5662
SLAS425B – JULY 2004 – REVISED MAY 2007 ................................................................................................................................................................ www.ti.com
Correct pairing of the I- and Q-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect
to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
Figure 19. Single-Bus Interleaved Mode Operation
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