Datasheet

Dual-Bus Data Interface and Timing
Valid Data
D[11:0]
t
su
t
h
t
lat
t
pd
t
settle
WRT1/
WRT2
CLK1/
CLK2
IOUT
or
IOUT
t
1ph
Single-Bus Interleaved Data Interface and Timing
DAC5662
www.ti.com ................................................................................................................................................................ SLAS425B – JULY 2004 – REVISED MAY 2007
Table 1. Operating Modes
MODE PIN Mode pin connected to DGND Mode pin connected to DVDD
Bus input Single-bus interleaved mode, clock and write input equal for both Dual-bus mode, DACs operate
DACs independently
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5662 consist
of two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,
WRTB) and clock (CLKA, CLKB) lines. The WRT lines control the channel input latches and the CLK lines
control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5662. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLK must occur at the same time or before the rising edge of the
WRT signal. A minimum delay of 2 ns should be maintained if the rising edge of the clock occurs after the rising
edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRT and CLK lines connected together.
Figure 18. Dual Bus Mode Operation
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 19 shows the timing diagram. In
interleaved mode, the I- and Q-channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the I-channel input bus to either the I-channel input latch
(SELECTIQ is high) or to the Q-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data value
in the Q-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is low,
the data value in the I-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the I-channel input data rate is twice the update rate of the DAC core. As in dual-bus mode,
it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch the I-
and Q-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the I- and
Q-DAC latches on the following falling edge of the write inputs. The DAC5662 clock input is divided by a factor of
two before it is presented to the DAC latches.
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): DAC5662