Datasheet

Digital Inputs and Timing
Digital Inputs
DA[11:0]
DB[11:0]
SLEEP
CLKA/B
WRTA/B
Internal
DigitalIn
DVDD
400W
100kW
DGND
GSET
MODE
Internal
DigitalIn
DVDD
400W
100kW
DGND
Input Interfaces
DAC5662
SLAS425B – JULY 2004 – REVISED MAY 2007 ................................................................................................................................................................ www.ti.com
The data input ports of the DAC5662 accept a standard positive coding with data bit D11 being the most
significant bit (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance will
typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long
as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified
limits.
All digital inputs of the DAC5662 are CMOS compatible. Figure 16 and Figure 17 show schematics of the
equivalent CMOS digital inputs of the DAC5662. The pullup and pulldown circuitry is approximately equivalent to
100k Ω . The 12-bit digital data input follows the offset positive binary coding scheme. The DAC5662 is designed
to operate with a digital supply (DVDD) of 3 V to 3.6 V.
Figure 16. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
The DAC5662 features two operating modes selected by the MODE pin, as shown in Table 1 .
• For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
• In single-bus interleaved mode, the data should be presented interleaved at the I-channel input bus. The
Q-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
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