User’s Guide 2006 Wireless Infrastructure SLAU139B
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the specified input and output voltage ranges described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Information About Cautions and Warnings Preface Read This First About This Manual How to Use This Manual This document contains the following chapters: - Chapter 1 − Introduction - Chapter 2 −Circuit Description - Chapter 3 − Physical Description and Parts List - Chapter 4 − Schematics Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement.
Contents FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Power Requirements . . . . . . . . . . . . . . . . . .
Contents Figures 3−1 3−2 3−3 3−4 Top Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 2, Ground Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 3, Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 4, Bottom Layer . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This user’s guide document gives a general overview of the DAC5672/62/52 evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. Topic Page 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Power Requirements . . .
Purpose 1.1 Purpose The DAC5672/62/52 EVM provides a platform for evaluating the DAC5672/62/52 digital-to-analog converter (DAC) family under various signal, reference, and supply conditions. This document should be used in combination with the EVM schematic diagram supplied. 1.2 EVM Basic Functions Digital inputs to the DAC can be provided with CMOS level signals up to 275 MSPS through two 34-pin headers. This enables the user to provide high-speed digital data to the DAC5672/62/52.
DAC5672/62/52 EVM Operation Procedure 1.4 DAC5672/62/52 EVM Operation Procedure The DAC5672/62/52 EVM can be set up in a variety of configurations to accommodate a specific mode of operation. Before starting evaluation, the user should decide on the configuration and make the appropriate connections or changes. The demonstration board comes with following factory-set configuration: Single clock source mode using a clock input at J3.
1-4
Chapter 2 This chapter gives the circuit description including input clock, input data, output data, reference operations, and sleep mode operation. Topic Page 2.1 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic Diagram 2.1 Schematic Diagram The schematic diagram for the EVM is attached at the end of this document. 2.2 Circuit Function The following paragraphs describe the EVM circuits. 2.2.1 Input Clock The DAC5672/62/52 EVM default operation setting is with a single-ended input clock sent to the DAC5672/62/52. A 3 Vp-p, 1.5-V offset, 50% duty cycle external square wave is applied to SMA connector J3. This input represents a 50-Ω load to the source.
Circuit Function Table 2−2. Input Connector J10 2.2.3 J10 Pin No. Description J10 Pin No.
Circuit Function 2.2.4 Internal Reference Operation The full-scale output current is set by applying an external resistor (Rset) between the BIASJ pins of the DAC5672/62/52 and ground. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying Rset or changing the externally applied reference voltage. The full-scale output current, IOUTFS, is defined as follows: IOUT FS + 32 ǒ V EXTIO R set Ǔ where VEXTIO is the voltage at pin EXTIO. This voltage is 1.
Chapter 3 This chapter describes the physcial characteristics and the PCB layout of the EVM and lists the components used on the module. Topic Page 3.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout 3.1 PCB Layout The EVM is constructed on a 4-layer, 5.1-inch x 4.8-inch, 0.062-inch thick PCB using FR−4 material. Figure 3−1 through Figure 3−4 show the PCB layout for the EVM. Figure 3−1.
PCB Layout Figure 3−2.
PCB Layout Figure 3−3.
PCB Layout Figure 3−4.
Parts List 3.2 Parts List Table 3−1 lists the parts used in constructing the EVM. Table 3−1. DAC5672/62/52 EVM Parts List Value Qty Part Number Vendor Ref Des Not Installed Capacitors 47 µF, tantalum, 10%, 10 V 2 10TPA47M Sanyo C16, C17 10 µF, 10 V, 10% capacitor 4 GRM42X5R106K10 Murata C6, C9, C10, C11 1 µF, 16 V, 10% capacitor 2 ECJ−3YB1C105K Panasonic C12, C13 0.01 µF, 50 V,5% capacitor 2 ECJ−2VB1H103K Panasonic C14, C15 0.
Chapter 4 Schematics The following pages contain the schematics for the EVM.
1 2 3 4 5 6 Revision History REV TP2 R10 (Note 1) 0 (Note 1) R9 C1 3 GSET R3 GSET (Sh 2) R7 2K 2 1 6 T1-1T R4 +3.3VA C7 49.9 W2 C3 SMA 0 (Note 1) 0 .1uF C21 (Note 1) (SH 2) MODE .1uF (Note 1) SLEEP MODE + .
1 2 3 DATA PORT 1 D 5 6 RP1 0 1 2 3 4 J9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 8 7 6 5 DA13 DA12 DA11 DA10 1 2 3 4 1 2 3 4 8 7 6 5 RP3 8 7 6 5 RP2 0 DA9 DA8 DA7 DA6 0 D DA5 DA4 DA3 DA2 +3.3VA J11 5X3X.1 RP4 0 DA1 DA0 3 4 6 7 9 10 12 13 15 8 7 6 5 4 3 2 34PIN_IDC 1 RP5 DA(0..13) MODE 2 DA(0..
