Datasheet

1
2
3
6
5
4
SYNC
SCLK
D
IN
V
OUT
GND
AV /V
DD REF
DAC5311
DAC6311
DAC7311
www.ti.com SBAS442B –AUGUST 2008–REVISED MAY 2013
PIN CONFIGURATION
DCK PACKAGE
SC70-6
(TOP VIEW)
Table 1. PIN DESCRIPTION
PIN NAME DESCRIPTION
Level-triggered control input (active low). This is the frame sychronization signal for the input data. When
SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the
1 SYNC following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this
edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by
the DACx311. Refer to the SYNC Interrupt section for more details.
2 SCLK Serial Clock Input. Data can be transferred at rates up to 50MHz.
Serial Data Input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock
3 D
IN
input.
4 AV
DD
/V
REF
Power Supply Input, +2.0V to 5.5V.
5 GND Ground reference point for all circuitry on the part.
6 V
OUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
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