Datasheet

SDIO
SCLK
SLEEP
TXENABLE
Internal
Digital In
GND
400 Ω 400 Ω
100 kΩ
100 kΩ
GND
IOVDD IOVDD
SDENB
RESETB
Internal
Digital In
S0027-03
LVDS
Receiver
DAC3484
GND
B0459-03
100 Ω
V
B
V
B
V
A
V
A
1.4 V
1 V
400 mV
0 V
–400 mV
1
0
V = (V + V )/2
COM A B
V
A, B
V
A, B
Logical Bit
Equivalent
Example
DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
Figure 86. LVDS Data Input Levels
Table 11. Example LVDS Data Input Levels
Resulting Differential Resulting Common-Mode
Applied Voltages
Logical Bit Binary
Voltage Voltage
Equivalent
V
A
V
B
V
A,B
V
COM
1.4 V 1.0 V 400 mV 1
1.2 V
1.0 V 1.4 V -400 mV 0
1.2 V 0.8 V 400 mV 1
1.0 V
0.8 V 1.2 V -400 mV 0
CMOS DIGITAL INPUTS
Figure 87 shows a schematic of the equivalent CMOS digital inputs of the DAC3484. SDIO, SCLK, SLEEP and
TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3484.
See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to
100kΩ.
Figure 87. CMOS Digital Equivalent Input
REFERENCE OPERATION
The DAC3484 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-
scale output current is set by applying an external resistor R
BIAS
to pin BIASJ. The bias current I
BIAS
through
resistor R
BIAS
is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 64 times this bias current and can thus be expressed as:
IOUT
FS
= 64 x I
BIAS
= 64 x (V
EXTIO
/ R
BIAS
) / 2
The DAC3484 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the
IOUT
FS
can be expressed as:
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