Datasheet

GND
Internal Digital In
IOVDD
LVDS
Receiver
S0516-01
100 Ω
C
0.1 F
AC
μ
C
0.1 F
AC
μ
Differential
ECL
or
(LV)PECL
Source
+
–
CLKIN
CLKINC
S0029-02
100 Ω
R
150
T
Ω
R
150
T
Ω
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
Figure 84 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
Figure 84. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source
LVDS INPUTS
The D[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N, and FRAMEP/N LVDS pairs have the input configuration
shown in Figure 85. Figure 86 shows the typical input levels and common-move voltage used to drive these
inputs.
Figure 85. D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS Input Configuration
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